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power management pf0100 applications ?tablets ?iptv ? industrial control ? medical monitoring ? home automation/ alarm/ energy management ep suffix (e-type) 56 qfn 8x8 98asa00405d consumer and industrial document order number: MMPF0100 rev. 3.0, 10/2012 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2012. all rights reserved. 14 channel configurable power management integrated circuit the pf0100 power management integr ated circuit (pmic) provides a highly programmable/ configurable ar chitecture, with fully integrated power devices and minimal external components. with up to six buck converters, six linear regulators, rtc supply, and coin-cell charger, the pf0100 can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. with on-chip one time programmable (otp) memory, the pf0100 is available in pre-programmed standard versions, or non-programmed to support custom programming. the pf0100 is especially suited to the i.mx6 family of devices and is supported by full system leve l reference designs, and pre- programmed versions of the device. features: ? four to six buck converters, depending on configuration ? single/ dual phase/ parallel options ? ddr termination tracking mode option ? boost regulator to 5.0 v out ? six general purpose linear regualtors ? programmable output voltage, sequence, and timing ? otp (one time programmable) memory for device configuration ? coin cell charger and rtc supply ? ddr termination reference voltage ? power control logic with processor interface and event detection ?i 2 c control ? individually programmable on, off, and standby modes vgen3 100 ma vgen5 100 ma camera audio codec cluster/hud external amp microphones speakers front usb pod rear usb pod rear seat infotaiment sensors i.mx6x i 2 c communication i 2 c communication pf0100 control signals parallel control/gpios licell charger coincell main supply 2.8 ? 4.5 v vgen1 100 ma vgen2 250 ma vgen4 350 ma vgen6 200 ma swbst 600 ma sw3a/b 2500 ma sw1c 2000 ma sw1a/b 2500 ma sw2 2000 ma sw4 1000 ma gps mipi upcie sata - flash nand - nor interfaces processor core voltages camera vrefddr ddr memory ddr memory interface sd-mmc/ nand mem. sata hdd wam gps mipi hdmi ldvs display usb ethernet can figure 1. simplified application diagram
analog integrated circuit device data 2 freescale semiconductor pf0100 table of contents 1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 part identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 format and fields description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.1 general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.2 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3.1 power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3.2 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 functional block requirements and b ehaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1.1 device start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1.2 one time programmability (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.3 otp prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.4 reading otp fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.5 programming otp fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 16 mhz and 32 khz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.1 internal core voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.2 vrefddr voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.2 state machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4.3 power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4.4 buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4.5 boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4.6 ldo regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.7 vsnvs ldo/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.5 control interface i2c block de scription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5.1 i2c device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5.2 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.4 interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.5.5 specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.5.6 register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1.2 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
analog integrated circuit device data freescale semiconductor 3 pf0100 8.2 pf0100 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.2.1 general board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.2.2 component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.2.3 general routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.2.4 parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.2.5 switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.3 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.3.1 rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.3.2 estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.1 packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.1 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.1 document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
analog integrated circuit device data 4 freescale semiconductor pf0100 orderable parts 1 orderable parts the pf0100 is available with both pre-programmed and non-pr ogrammed otp memory configurations. the non-programmed device uses "np" as the programming code. the pre-programmed devices are i dentified using the program codes from table 1 , which also list the associated freescale reference designs wh ere applicable. details of the ot p programming for each device can be found in table 9 . table 1. orderable part variations part number temperature (t a ) package programming reference designs notes MMPF0100npep -40 to 85 c 56 qfn 8x8 mm - 0.5 mm pitch e-type qfn (full lead) np n/a (2)(1) MMPF0100f0ep f0 mcimx6q-sdp mcimx6q-sdb mcimx6dl-sdp (2)(1) MMPF0100f1ep f1 mcimx6slevk (2)(1) MMPF0100f2ep f2 n/a (2)(1) notes 1. for tape and reel add an r2 suffix to the part number. 2. for programming details see table 9 .
analog integrated circuit device data freescale semiconductor 5 pf0100 part identification description 2 part identification this section provides an explanation of th e part numbers and their alphanumeric breakdown. 2.1 description part numbers for the chips have fields that identify the specific part configuration. you can use the values of these fields to determine the specific part you have received. 2.2 format and fields description the part number is structured in the following format: mm-ff-xxxx-yy-r-v-pp-rr table 2 shows the meaning and possible values for each field contai ned in the part number (not all combinations are valid). table 2. part number structure definition field definition possible values mm product category pm = prototype device mm = qualified standard device sm = custom device ff family pf = pf series xxxx product number 0100 yy program configuration see table 9 r revision blank for initial revision v variation blank for consumer and industrial pp package designator ep = e-type qfn exposed pad rr tape & reel indicator r2 = 13 inch reel hub
vin intb licell swbstfb swbstin swbstlx o/p drive swbst 600 ma boost pwron standby ictest scl sda vddio sw3a/b single/dual ddr 2500 ma buck vcoredig vcoreref sdwnb gndref sw1cfb sw1ain sw1c 2000 ma buck sw1fb sw1alx sw1blx sw1a/b single/dual 2500 ma buck sw1vsssns vsnvs vsnvs li cell charger resetbmcu sw2 2000 ma buck vgen1 100 ma vgen1 vin1 vgen2 250 ma vgen2 vgen3 100 ma vgen3 vin2 vgen4 350 ma vgen4 vgen5 100 ma vgen5 vin3 vgen6 200 ma vgen6 best of supply otp sw4 1000 ma buck vrefddr vddotp vinrefddr vhalf vcore pf0100 control clocks 32 khz and 16 mhz initialization state machine i 2 c interface clocks and resets i 2 c register map trim-in-package o/p drive o/p drive sw1bin sw1clx o/p drive sw1cin sw2fb sw2lx o/p drive sw2in sw2in sw3ain sw3afb sw3alx sw3blx o/p drive o/p drive sw3bin sw3bfb sw3vsssns sw4in sw4fb sw4lx o/p drive supplies control dvs control dvs control reference generation core control logic gndref1 analog integrated circuit device data 6 freescale semiconductor pf0100 internal block diagram format and fields description 3 internal block diagram figure 2. simplified internal block diagram
analog integrated circuit device data freescale semiconductor 7 pf0100 pin connections pinout diagram 4 pin connections 4.1 pinout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 43 44 45 46 47 48 49 50 51 52 53 54 55 56 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 intb sdwnb resetbmcu standby ictest sw1fb sw1ain sw1alx sw1blx sw1bin sw1clx sw1cin sw1cfb sw1vsssns licell vgen6 vin3 vgen5 sw3afb sw3ain sw3alx sw3blx sw3bin sw3bfb sw3vsssns vrefddr vinrefddr vhalf pwron vddio scl sda vcoreref vcoredig vin vcore gndref vddotp swbstlx swbstin swbstfb vsnvs gndref1 vgen1 vin1 vgen2 sw4fb sw4in sw4lx sw2lx sw2in sw2in sw2fb vgen3 vin2 vgen4 ep figure 3. pinout diagram
analog integrated circuit device data 8 freescale semiconductor pf0100 pin connections pin definitions 4.2 pin definitions table 3. pf0100 pin definitions pin number pin name pin function max rating type definition 1 intb o 3.6 v digital open drain interrupt signal to processor 2 sdwnb o 3.6 v digital open drain signal to indicate an imminent system shutdown 3 resetbmcu o 3.6 v digital open drain reset output to processo r. alternatively can be used as a power good output. 4 standby i 3.6 v digital standby input signal from processor 5 ictest i 7.5 v digital/ analog reserved pin. connect to gnd in application. 6 sw1fb i 3.6 v analog output voltage feedback for sw1a /b. route this trace separately from the high current path and terminate at the output capacitance. 7 sw1ain i 4.8 v analog input to sw1a regulator. bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. 8 sw1alx o 4.8 v analog regulator 1a switch node connection 9 sw1blx o 4.8 v analog regulator 1b switch node connection 10 sw1bin i 4.8 v analog input to sw1b regulator. bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. 11 sw1clx o 4.8 v analog regulator 1c switch node connection 12 sw1cin i 4.8 v analog input to sw1c regulator. bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. 13 sw1cfb i 3.6v analog output voltage feedback for sw1c. route this trace separately from the high current path and terminate at the output capacitance. 14 sw1vsssns gnd - gnd ground reference for regulat ors sw1abc. it is connected externally to gndref through a board ground plane. 15 gndref1 gnd - gnd ground reference for regulators sw2 and sw4. it is connected externally to gndref, via board ground plane. 16 vgen1 o 2.5 v analog vgen1 regulator output, bypass with a 2.2 p f ceramic output capacitor. 17 vin1 i 3.6 v analog vgen1, 2 input supply. bypass with a 1.0 p f decoupling capacitor as close to the pin as possible. 18 vgen2 o 2.5 v analog vgen2 regulator output, bypass with a 4.7 p f ceramic output capacitor. 19 sw4fb i 3.6 v analog output voltage feedback for sw4. route this trace separately from the high current path and terminate at the output capacitance. 20 sw4in i 4.8 v analog input to sw4 regulator. bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. 21 sw4lx o 4.8 v analog regulator 4 switch node connection 22 sw2lx o 4.8 v analog regulator 2 switch node connection
analog integrated circuit device data freescale semiconductor 9 pf0100 pin connections pin definitions 23 sw2in i 4.8 v analog input to sw2 regulator . connect pin 23 together with pin 24 and bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to these pins as possible. 24 sw2in i 4.8 v analog 25 sw2fb i 3.6 v analog output voltage feedback for sw2. route this trace separately from the high current path and terminate at the output capacitance. 26 vgen3 o 3.6 v analog vgen3 regulator output. bypass with a 2.2 p f ceramic output capacitor. 27 vin2 i 3.6 v analog vgen3,4 input. bypass with a 1.0 p f decoupling capacitor as close to the pin as possible. 28 vgen4 o 3.6 v analog vgen4 regulator output, bypass with a 4.7 p f ceramic output capacitor. 29 vhalf i 3.6 v analog half supply reference for vrefddr 30 vinrefddr i 3.6 v analog vrefddr regulator input. bypass with at least 1.0 p f decoupling capacitor as close to the pin as possible. 31 vrefddr o 3.6 v analog vrefddr regulator output 32 sw3vsssns gnd - gnd ground reference for the sw3 regulator. connect to gndref externally via the board ground plane. 33 sw3bfb i 3.6 v analog output voltage feedback for sw3b. route this trace separately from the high current path and terminate at the output capacitance. 34 sw3bin i 4.8 v analog input to sw3b regulator. bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. 35 sw3blx o 4.8 v analog regulator 3b switch node connection 36 sw3alx o 4.8 v analog regulator 3a switch node connection 37 sw3ain i 4.8 v analog input to sw3a regulator. bypass with at least a 4.7 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. 38 sw3afb i 3.6 v analog output voltage feedback for sw3a. route this trace separately from the high current path and terminate at the output capacitance. 39 vgen5 o 3.6 v analog vgen5 regulator output. bypass with a 2.2 p f ceramic output capacitor. 40 vin3 i 4.8 v analog vgen5, 6 input. bypass with a 1.0 p f decoupling capacitor as close to the pin as possible. 41 vgen6 o 3.6 v analog vgen6 regulator output. by pass with a 2.2 p f ceramic output capacitor. 42 licell i/o 3.6 v analog coin cell supply input/output 43 vsnvs o 3.6 v analog ldo or coin cell output to processor 44 swbstfb i 4.8 v analog boost regulator feedback. connect th is pin to the output rail close to the load. keep this trace away from other noisy traces and planes. 45 swbstin i 4.8 v analog input to swbst regulator. bypass with at least a 2.2 p f ceramic capacitor and a 0.1 p f decoupling capacitor as close to the pin as possible. table 3. pf0100 pin definitions (continued) pin number pin name pin function max rating type definition
analog integrated circuit device data 10 freescale semiconductor pf0100 pin connections pin definitions 46 swbstlx o 7.5 v analog swbst switch node connection 47 vddotp i 9.0 v (3) digital & analog supply to program otp fuses 48 gndref gnd - gnd ground reference for the main band gap regulator. 49 vcore o 3.6 v analog analog core supply 50 vin i 4.8 v analog main chip supply 51 vcoredig o 1.5 v analog digital core supply 52 vcoreref o 1.5 v analog main band gap reference 53 sda i/o 3.6 v digital i 2 c data line (open drain) 54 scl i 3.6 v digital i 2 c clock 55 vddio i 3.6 v analog supply for i 2 c bus 56 pwron i 3.6 v digital power on/off from processor - ep gnd - gnd expose pad. functions as ground re turn for buck regulators. tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. notes 3. 9.0 v maximum voltage rating during otp fuse pr ogramming. 7.5 v maximum dc voltage rated otherwise. table 3. pf0100 pin definitions (continued) pin number pin name pin function max rating type definition
analog integrated circuit device data freescale semiconductor 11 pf0100 general product characteristics absolute maximum ratings 5 general product characteristics 5.1 absolute maximum ratings table 4. absolute maximum ratings all voltages are with respect to ground, unless otherwise noted. exceeding these ratings may cause malfunction or permanent damage to the device. the detailed maximum voltage ra ting per pin can be found in the pin list section. symbol description value unit electrical ratings v in main input supply voltage -0.3 to 4.8 v v ddotp otp programming input supply voltage -0.3 to 9.0 v v licell coin cell voltage -0.3 to 3.6 v v esd esd ratings human body model (4) charge device model (4) 2000 500 v notes 4. esd testing is performed in accordance with the human body model (hbm) (czap = 100 pf, rzap = 1500 : ), and the charge device model (cdm), robotic (czap = 4.0 pf).
analog integrated circuit device data 12 freescale semiconductor pf0100 general product characteristics thermal characteristics 5.2 thermal characteristics 5.2.1 power dissipation during operation, the temperature of the die should not exceed the operating junc tion temperature noted in table 5 . to optimize the thermal management and to avoid overheatin g, the pf0100 provides thermal protection. an internal comparator monitors the die temperature. interrupts therm110i, therm120i, therm125 i, and therm130i will be generated when the respective thresholds specified in table 6 are crossed in either direction. the temperature range can be determined by reading the thermxxxs bits in register intsense0. in the event of excessive power dissipation, thermal protection circuitry will shut down the pf0100. this thermal protection wi ll act above the thermal protection threshold listed in table 6 . to avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. this protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protecti on is not tripped under normal conditions. table 5. thermal ratings symbol description (rating) min. max. unit thermal ratings t a ambient operating temperature range -40 85 q c t j operating junction temperature range (5) -40 125 q c t st storage temperature range -65 150 q c t pprt peak package reflow temperature (6)(7) ? note 7 q c qfn56 thermal resistance and package dissipation ratings r t ja junction to ambient (8)(9)(10) natural convection four layer board (2s2p) eight layer board (2s6p) ? ? 28 15 c/w r t jma junction to ambient (@200 ft/min) (8)(10) four layer board (2s2p) ? 22 c/w r t jb junction to board (11) ?10c/w r 4 jcbottom junction to case bottom (12) ? 1.2 c/w < jt junction to package top (13) natural convection ? 2.0 c/w notes 5. do not operate beyond 125 c for extended periods of time. see table 6 for thermal protection features. 6. pin soldering temperature limit is for 10 seconds maximum durat ion. not designed for immersion soldering. exceeding these lim its may cause a malfunction or permanent damage to the device. 7. freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i.e. mc33xxxd enter 33xxx), and review parametrics. 8. junction temperature is a function of die size, on-chip power dissipation, package thermal resi stance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other component s on the board, and board thermal resistance. 9. the board uses the jedec specifications for th ermal testing (and simulation) jesd51-7 and jesd51-5. 10. per jedec jesd51-6 with the board horizontal. 11. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. 12. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1 ). 13. thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature pe r jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt.
analog integrated circuit device data freescale semiconductor 13 pf0100 general product characteristics electrical characteristics 5.3 electrical characteristics 5.3.1 general specifications table 6. thermal protection thresholds parameter min typ max units thermal 110 c threshold (therm110) 100 110 120 c thermal 120 c threshold (therm120) 110 120 130 c thermal 125 c threshold (therm125) 115 125 135 c thermal 130 c threshold (therm130) 120 130 140 c thermal warning hysteresis 2.0 ? 4.0 c thermal protection threshold 130 140 150 c table 7. general pmic static characteristics. t a = -40 to 85 c, vin = 2.8 to 4.5 v, vddio = 1.7 to 3.6 v, typi cal external component values and full load current range, unles s otherwise noted. pin name parameter load condition min max unit pwron v il ?0.00.2 * vsnvsv v ih ? 0.8 * vsnvs 3.6 v resetbmcu v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7* vin vin v scl v il ? 0.0 0.2 * vddio v v ih ? 0.8 * vddio 3.6 v sda v il ? 0.0 0.2 * vddio v v ih ? 0.8 * vddio 3.6 v v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7*vddio vddio v intb v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7* vin vin v sdwnb v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7* vin vin v standby v il ?0.00.2 * vsnvsv v ih ? 0.8 * vsnvs 3.6 v vddotp v il ?0.00.3v v ih ?1.11.7v
analog integrated circuit device data 14 freescale semiconductor pf0100 general product characteristics electrical characteristics 5.3.2 current consumption the current consumption of the individual blocks is described in detail through out this specification. for convenience, a summa ry table follows for standard use cases. table 8. current consumption summary t a = -40 to 85 c, vin = 3.6 v, vddio = 1.7 to 3.6 v, licell = 1.8 to 3. 3 v, vsnvs = 3.0 v, typical external component values, unless otherwise noted. typical values are characterized at vin = 3.6 v, vddio = 3.3 v, li cell = 3.0 v, vsnvs = 3.0 v and 25 c, unless otherwise noted. mode pf0100 conditions system conditions typical max unit coin cell (14) vsnvs from licell all other blocks off vin = 0.0 v vsnvsvolt[2:0] = 110 no load on vsnvs 5.0 7.0 p a off (14)(15) vsnvs from vin or licell wake-up from pwron active 32 k rc on all other blocks off vin t uvdet no load on vsnvs, pmic able to wake-up 16 21 p a sleep vsnvs from vin wake-up from pwron active trimmed reference active sw3a/b pfm trimmed 16 mhz rc off 32 k rc on vrefddr disabled no load on vsnvs. ddr memories in self refresh 122 220 p a standby vsnvs from either vin or licell sw1a/b combined in pfm sw1c in pfm sw2 in pfm sw3a/b combined in pfm sw4 in pfm swbst off trimmed 16 mhz rc enabled trimmed reference active vgen1-6 enabled vrefddr enabled no load on vsnvs. processor enabled in low power mode. all rails powered on except boost (load = 0 ma) 297 420 p a notes 14. at 25 c only. 15. when vin is below the uvdet threshold, in the range of 1.8 v d vin < 2.65 v, the quiescent current increases by 50 p a, typically.
analog integrated circuit device data freescale semiconductor 15 pf0100 general description features 6 general description the pf0100 is the power management integrated circuit (pmic) designed primarily for use with freescale?s i.mx6 series of application processors. 6.1 features this section summarizes the pf0100 features. ? input voltage range to pmic: 2.8 - 4.5 v ? buck regulators ? four to six channel configurable ? sw1a/b/c, 4.5 a (single); 0.3 to 1.875 v ? sw1a/b, 2.5 a (single/dual); sw1c 2.0 a (independent); 0.3 to 1.875 v ?sw2, 2.0 a; 0.4 to 3.3 v ? sw3a/b, 2.5 a (single/dual); 0.4 to 3.3 v ? sw3a, 1.25 a (independent); sw3b, 1.25 a (independent); 0.4 to 3.3 v ?sw4, 1.0 a; 0.4 to 3.3 v ? sw4, vtt mode provide ddr termination at 50% of sw3a ? dynamic voltage scaling ? modes: pwm, pfm, aps ? programmable output voltage ? programmable current limit ? programmable soft start ? programmable pwm switching frequency ? programmable ocp with fault interrupt ? boost regulator ? swbst, 5.0 to 5.15 v, 0.6 a, otg support ? modes: pfm and auto ? ocp fault interrupt ?ldos ? six user programable ldo ? vgen1, 0.80 to 1.55 v, 100 ma ? vgen2, 0.80 to 1.55 v, 250 ma ? vgen3, 1.8 to 3.3 v, 100 ma ? vgen4, 1.8 to 3.3 v, 350 ma ? vgen5, 1.8 to 3.3 v, 100 ma ? vgen6, 1.8 to 3.3 v, 200 ma ? soft start ? ldo/switch supply ? vsnvs (1.0/1.1/1 .2/1.3/1.5/1.8/3.0 v), 400 p a ? ddr memory reference voltage ? vrefddr, 0.6 to 0.9 v, 10 ma ?16 mhz internal master clock ? otp(one time programmable) me mory for device configuration ? user programmable start-up sequence and timing ? battery backed memory including coin cell charger ?i 2 c interface ? user programmable standby, sleep, and off modes
analog integrated circuit device data 16 freescale semiconductor pf0100 general description functional block diagram 6.2 functional block diagram logic and control switching regulators sw1a/b/c (0.3 to 1.875v) configurable 4.5a or 2.5a+2.0a linear regulators sw2 (0.4 to 3.3v, 2a) sw3a/b (2.5a) (0.4 to 3.3v) configurable 2.5a or 1.25a+1.25a sw4 (0.4 to 3.3v, 1a) boost regulator (5 to 5.15v, 600ma) usb otg supply vgen1 (0.8 to 1.55v, 100ma) vgen2 (0.8 to 1.55v, 250ma) vgen3 (1.8 to 3.3v, 100ma) vgen4 (1.8 to 3.3v, 350ma) vgen5 (1.8 to 3.3v, 100ma) vgen6 (1.8 to 3.3v, 200ma) bias & references parallel mcu interface regulator control vsnvs (1.0 to 3.0v, 400ua) rtc supply with coin cell charger MMPF0100 functional internal block diagram i 2 c communication & registers power generation fault detection and protection ddr voltage reference current limit short-circuit internal core voltage reference thermal otp startup configuration sequence and timing otp prototyping (try before buy) voltage power stage figure 4. functional block diagram 6.3 functional description 6.3.1 power generation the pf0100 pmic features four buck regulators (up to six ind ependent outputs), one boost regulat or, six general purpose ldos, one switch/ldo combination and a ddr voltage reference to s upply voltages for the applicat ion processor and peripheral devices. the number of independent buck regulator output s ca n be configured from four to six, thereby providing flexibility to operate w ith higher current capability, or to operate as independent outputs for applications requiring more voltage rails with lower curren t demands. further, sw1 and sw3 regulators can be configured as single/dual phase and/or indepe ndent converters. one of the buck regulators, sw4, can also operate as a tracking regulator when used for memory termination. the buck regulators provide the supply to processor cores and to other low voltage circuits such as io and memory. dynamic voltage scaling is provided to allow controlled supply rail adjustments for t he processor cores and/or other circuitry. depending on the system power path configuration, the six general purpose ldo regulators can be directly supplied from the main input supply or from the switching regul ators to power peripherals, such as audio, camera, bluetooth, wireless lan, etc. a specific vrefddr voltage reference is included to provide a ccurate reference voltage for ddr memories operating with or without vtt termination. the vsnvs block b ehaves as an ldo, or as a bypass switch to supply the snvs/srtc circuitry on the i.mx processors; vsnvs may be powe red from vin, or from a coin cell. 6.3.2 control logic the pf0100 pmic is fully programmable via the i 2 c interface. additional communication is provided by direct logic interfacing including interrupt and reset. start-up sequence of the device is selected upon the initial otp configuration explained in the start- up section, or by configuring the ?try befo re buy? feature to test different power up sequences before choosing the final otp configuration. the pf0100 pmic has the interfaces for the power buttons and ded icated sig naling interfacing with the processor. it also ensure s supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. a charger for the coin cell is included as well.
analog integrated circuit device data freescale semiconductor 17 pf0100 general description functional description 6.3.2.1 interface signals pwron pwron is an input signal to the ic that generates a turn-on even t. it can be configured to detect a level, or an edge using the pwron_cfg bit. refer to section turn on events for more details. standby standby is an input signal to the ic. when it is asserted the part enters standby mode and w hen de-asserted, the part exits standby mode. standby can be configured as active high or active low using the standbyinv bit. refer to the section standby mode for more details. note: when operating the pmic at vin d 2.85 v and vsnvs is programmed for a 3.0 v output, a coin cell must be present to provide vsnvs, or the pmic will not reli ably enter and exit the standby mode. resetbmcu resetbmcu is an open-drain, active low out put configurable for two modes of operation. in its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to figure 5 as an example. in this mode, the signal can be used to bring the processor out of re set, or as an indicator that all supplies have been enabled; it is only asserted fo r a turn-off event. when configured for its fault mode, resetbm cu is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. at anytime, if a fault occurs and persists for 1.8 ms typically, resetbmcu is asserted, low. the pf0100 is turned off if the fault persists for more than 100 ms typically. the pwron signal rest arts the part, though if the fault persists, the sequence described above will be repeated. to enter the fault mode, set bit otp_pg_en of register otp pwrgd en to ?1?. this regist er, 0xe8, is located on extended page 1 of the register map. to test the fault mode, the bit may be set during tbb prototyping, or the mode ma y be permanently chosen by programming otp fuses. sdwnb sdwnb is an open-drain, active low output that notifies the processor of an imminent pmic shut down. it is asserted low for one 32 khz clock cycle before powering down and is then de-asserted in the off state. intb intb is an open-drain, active low output. it is asserted when any fault occurs, provided that the fault interrupt is unmasked. intb is de-asserted after the fault interrupt is cleared by software, which requires writing a ?1? to the fault interrupt bit.
analog integrated circuit device data 18 freescale semiconductor pf0100 functional block requi rements and behaviors start-up 7 functional block requirements and behaviors 7.1 start-up the pf0100 can be configured to start-up fr om either the internal otp configuration, or with a hard-coded configuration built i n to the device. the internal hard-coded configuration is enabled by connecting the vddotp pin to vcoredig through a 100kohm resistor. the otp configuration is enabled by connecting vcoredig to gnd. for np devices, selecting the otp configuration causes the pf0100 to not start-up. however, the pf0100 can be controlled through the i2c port for prototyping and programming. once programmed, the np device will startup with the customer programmed configuration. 7.1.1 device start-up configuration table 9 shows the default configuration which can be accessed on all devices as described above, as well as the pre- programmed otp configurations. table 9. start-up configuration registers default configuration pre-programmed otp configuration all devices f0 f1 f2 default i 2 c address 0x08 0x08 0x08 0x08 vsnvs_volt 3.0 v 3.0 v 3.0 v 3.0 v sw1ab_volt 1.375 v 1.375 v 1.375 v 1.375 v sw1ab_seq 1 1 1 1 sw1c_volt 1.375 v 1.375 v 1.375 v 1.375 v sw1c_seq 1 2 1 1 sw2_volt 3.0 v 3.3 v 3.15 v 3.15 v sw2_seq 2 5 2 2 sw3a_volt 1.5 v 1.5 v 1.2 v 1.5 v sw3a_seq 3 3 4 4 sw3b_volt 1.5 v 1.5 v 1.2 v 1.5 v sw3b_seq 3 3 4 4 sw4_volt 1.8 v 3.15 v 1.8 v 1.8 v sw4_seq 3 6 3 3 swbst_volt - 5.0 v 5.0 v 5.0 v swbst_seq - 13 6 6 vrefddr_volt 0.75 v 0.75 v 0.6 v 0.75 v vrefddr_seq 3 3 4 4 vgen1_volt - 1.5 v 1.2 v 1.2 v vgen1_seq - 9 4 4 vgen2_volt 1.5 v 1.5 v - - vgen2_seq 2 10 - - vgen3_volt - 2.5 v - - vgen3_seq - 11 - -
analog integrated circuit device data freescale semiconductor 19 pf0100 functional block requirements and behaviors start-up vgen4_volt 1.8 v 1.8 v 1.8 v 1.8 v vgen4_seq 3 7 3 3 vgen5_volt 2.5 v 2.8 v 2.5 v 2.5 v vgen5_seq 3 12 5 5 vgen6_volt 2.8 v 3.3 v - - vgen6_seq 3 8 - - pu config, seq_clk_speed 1.0 ms 2.0 ms 1.0 ms 1.0 ms pu config, swdvs_clk 6.25 mv/ p s 1.5625 mv/ p s 12.5 mv/ p s12.5 mv/ p s pu config, pwron level sensitive sw1ab config sw1ab single phase, sw1c independent mode, 2.0 mhz sw1c config 2.0 mhz sw2 config 2.0 mhz sw3a config sw3ab single phase, 2.0 mhz sw3b config 2.0 mhz sw4 config no vtt, 2.0 mhz pg en resetbmcu in default mode table 9. start-up configuration registers default configuration pre-programmed otp configuration all devices f0 f1 f2
*vsnvs will start from 1.0 v if licell is valid before vin. uvdet licell vin vsnvs pwron sw1a/b sw1c sw2 vgen2 sw3a/b sw4 vrefddr vgen4 vgen5 vgen6 resetbmcu td 1 td 3 td 4 td 4 tr 1 tr 3 tr 3 tr 3 td 5 tr 4 tr 2 td 2 1v analog integrated circuit device data 20 freescale semiconductor pf0100 functional block requi rements and behaviors start-up figure 5. default start-up sequence table 10. default start-up sequence timing parameter description min typ max unit t d1 turn-on delay of vsnvs (16) ?15?ms t r1 rise time of vsnvs ? 3.0 ? ms t d2 user determined delay ? 1.0 ? ms t r2 rise time of pwron ? (17) ?ms t d3 turn-on delay of first regulator seq_clk_speed[1:0] = 00 ? 2.0 ? ms seq_clk_speed[1:0] = 01 (18) ?2.5? seq_clk_speed[1:0] = 10 ? 4.0 ? seq_clk_speed[1:0] = 11 ? 7.0 ?
analog integrated circuit device data freescale semiconductor 21 pf0100 functional block requirements and behaviors start-up 7.1.2 one time prog rammability (otp) otp allows the programming of start-up conf igurations for a variety of applications. before permanently programming the ic by programming fuses, a configuration may be prototyped by using th e ?try before buy? (tbb) feat ure. further, an error correction code(ecc) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. the parameters that can be confi gured by otp are listed below. ? general: i 2 c slave address, pwron pin configur ation, start-up sequence and timing ? buck regulators: output voltage, dual/single phase or i ndependent mode configuration, s witching frequency, and soft start ramp rate ? boost regulator and ldos: output voltage note: when prototyping or programming fuses, the user must ensure that register settings are consistent with the hardware configuration. this is most important fo r the buck regulators, where the quantity, si ze, and value of the inductors depend on t he configuration (single/dual phase or independent mode) and the swit ching frequency. additionally, if an ldo is powered by a buck regulator, it will be gated by the buck regulator in the start-up sequence. 7.1.2.1 start-up sequence and timing each regulator has 5-bits allocated to program its start-up time slot from a turn on event; ther efore, each can be placed from position one to thirty-one in the start-up sequence. the all zeros code indicates that a regulator is not part of the start-up sequence and will remain off. see table 11 . the delay between each position is equal; ho wever, four delay options are available. see table 12 . the start-up sequence will terminate at the last programmed regulator. t r3 rise time of regulators (19) ?0.2?ms t d4 delay between regulators seq_clk_speed[1:0] = 00 ? 0.5 ? ms seq_clk_speed[1:0] = 01 ? 1.0 ? seq_clk_speed[1:0] = 10 ? 2.0 ? seq_clk_speed[1:0] = 11 ? 4.0 ? t r4 rise time of resetbmcu ? 0.2 ? ms t d5 turn-on delay of resetbmcu ? 2.0 ? ms notes 16. assumes licell voltage is valid before vin is applied. if licell is not valid before vin is applied then vsnvs turn-on delay may extend to a maximum of 24 ms. 17. depends on the external signal driving pwron. 18. default configuration. 19. rise time is a function of slew rate of regulators and nominal voltage selected. table 10. default start-up sequence timing parameter description min typ max unit
analog integrated circuit device data 22 freescale semiconductor pf0100 functional block requi rements and behaviors start-up 7.1.2.2 pwron pin configuration the pwron pin can be configured as either a level sensit ive input (pwron_cfg = 0), or as an edge sensitive input (pwron_cfg = 1). as a level sensitive input , an active high signal turns on the part and an active low signal turns off the par t, or puts it into sleep mode. as an edge sensitive input, such as when connected to a mechanical switch, a falling edge will turn on the part and if the switch is held low fo r greater than or equal to 4.0 seconds, the part will turn off or enter sleep mode. 7.1.2.3 i 2 c address configuration the i 2 c device address can be programmed from 0x08 to 0x0f. this allows flexibility to change the i 2 c address to avoid bus conflicts. address bit, i2c_slv_addr[3] in otp_i2c_addr register is hard coded to ?1? while the lower three lsbs of the i 2 c address (i2c_slv_addr[2:0]) are programmable as shown in table 14 . table 11. start-up sequence swxx_seq[4:0]/ vgenx_seq[4:0]/ vrefddr_seq[4:0] sequence 00000 off 00001 seq_clk_speed[1:0] * 1 00010 seq_clk_speed[1:0] * 2 ** ** ** ** 11111 seq_clk_speed[1:0] * 31 table 12. start-up sequence clock speed seq_clk_speed[1:0] time ( p s) 00 500 01 1000 10 2000 11 4000 table 13. pwron configuration pwron_cfg mode 0 pwron pin high = on pwron pin low = off or sleep mode 1 pwron pin pulled low momentarily = on pwron pin low for 4.0 se conds = off or sleep mode table 14. i 2 c address configuration i2c_slv_addr[3] hard coded i2c_slv_addr[2:0] i 2 c device address (hex) 1 000 0x08 1 001 0x09 1 010 0x0a
analog integrated circuit device data freescale semiconductor 23 pf0100 functional block requirements and behaviors start-up 7.1.2.4 soft start ramp rate the start-up ramp rate or soft st art ramp rate can be chosen from the same options as shown in dynamic voltage scaling . 7.1.3 otp prototyping before permanently programming fuse s, it is possible to test the desired configurat ion by using the ?try before buy? feature. w ith this feature, the configuration is loaded fr om the otp registers. these registers mere ly serve as temporary storage for the val ues to be written to the fuses, for the values read from the fuses, or for the values read from the default configuration. to avoid confusion, these registers will be referred to as the tbbotp registers. the portion of the register map that concerns otp is shown in table 136 and table 137 . the contents of the tbbotp registers are initialized to zero when a valid vin is first applied. the values that are then loaded into the tbbotp registers depend on the setting of the vddotp pin and on the value of the tbb_por and fuse_por bits. refer to table 15 . ? if vddotp = vcoredig (1.5 v), the values are loaded from the default configuration. ? if vddotp = 0.0 v, tbb_por = 0 and fuse_por = 1, the values are loaded from the fuses. ? if vddotp = 0.0 v, tbb_por = 0 and fuse_por = 0, the tbbotp registers remain initialized at zero. the initial value of tbb_por is a lways ?0?; only when vddotp = 0.0 v and tbb_por is set to ?1? are the values from the tbbotp registers maintained and not loaded from a different source. the contents of the tbbotp r egisters are modified by i 2 c. to communicate with i 2 c, vin must be valid and vddio, to which sda and scl are pulled up, must be powered by a 1.7 to 3.6 v supply. vin, or the coin cell vo ltage must be valid to maintain the contents of the registers. to power on with the contents of the t bbotp registers, the following conditions must exist; vin is valid, vddotp = 0.0 v, tbb_por = 1 and there is a valid turn -on event. refer to the application note an4536 for an example of prototyping. 7.1.4 reading otp fuses as described in the previous section, the contents of the fu ses are loaded to the tbbotp registers when the following condition s are met; vin is valid, vddotp = 0.0 v, tbb_por = 0 and fuse_por = 1. if ecc were enabled at the time the fuses were programmed, the error corrected values can be loaded into the tbbotp registers if desired. once the fuses are loaded and a turn-on event occurs, the pmic will power on with the configurati on programmed in the fuses. for more details on reading the otp fuses, see application note an4536 . 7.1.5 programming otp fuses the parameters that can be programmed are shown in the tbbotp registers in the extended page 1 of the register map. the pf0100 offers ecc as well as automated programming, or man ual programming. the control regi sters for these functions are located in extended page 2 of the register map. there ar e ten banks of twenty-six fuses each that can be programmed. programming the fuses requires an 8.25 v, 100 ma supply powering the vddotp pin, bypassed with 10 to 20 p f of capacitance. for more details on programming the otp fuses, see application note an4536 . 1 011 0x0b 1 100 0x0c 1 101 0x0d 1 110 0x0e 1 111 0x0f table 14. i 2 c address configuration i2c_slv_addr[3] hard coded i2c_slv_addr[2:0] i 2 c device address (hex)
analog integrated circuit device data 24 freescale semiconductor pf0100 functional block requi rements and behaviors 16 mhz and 32 khz clocks 7.2 16 mhz and 32 khz clocks there are two clocks: a trimmed 16 mhz, rc oscillator and an untrimmed 32 khz, rc oscillator. the 16 mhz oscillator is specified within -8.0/+5.0%. the 32 khz untrimmed clock is only used in the following conditions: ? vin < uvdet ? all regulators are in sleep mode ? all regulators are in pfm switching mode a 32 khz clock, derived from the 16 mhz trimmed clock, is used when accurate timing is needed under the following conditions: ? during start-up, vin > uvdet ? pwron_cfg = 1, for power button debounce timing in addition, when the 16 mhz is active in the on mode, the debounce times in table 26 are referenced to the 32 khz derived from the 16 mhz clock. the exceptions are the lowvini and pw roni interrupts, which are referenced to the 32 khz untrimmed clock. 7.3 bias and references block description 7.3.1 internal core voltage references all regulators use the main bandgap as the reference. the main bandgap is bypassed with a capacitor at vcoreref. the bandgap and the rest of the core circuitry are supplied from vcor e. the performance of the regul ators is directly dependent on the performance of the bandgap. no external dc loading is al lowed on vcore, vcoredig, or vcoreref. vcoredig is kept powered as long as there is a valid supply and/or valid coin cell. table 17 shows the main characteristics of the core circuitry. table 15. source of start-up sequence vddotp(v) tbb_por fuse_por start-up sequence 0 0 0 none 0 0 1 otp fuses 0 1 x tbbotp registers 1.5 x x factory defined table 16. 16 mhz clock specifications t a = -40 to 85c, v in = 2.8 to 4.5 v, licell = 1.8 to 3.3 v and typical external component values. typical values are characterized at v in = 3.6 v, licell = 3.0 v, and 25 c, unless otherwise noted. parameters symbol min typ max units operating voltage from vin v in16mhz 2.8 ? 4.5 v frequency f 16mhz 14.7 16 16.8 mhz
analog integrated circuit device data freescale semiconductor 25 pf0100 functional block requirements and behaviors bias and references block description 7.3.1.1 external components 7.3.2 vrefddr voltage reference vrefddr is an internal pmos half supply voltage follower capable of supplying up to 10 ma. the output voltage is at one half the input voltage. its typically used as th e reference voltage for ddr memories. a filter ed resistor divider is utilized to cre ate a low frequency pole. this divider then utilizes a voltage follower to drive the load. table 17. core voltages electrical specifications (21) t a = -40 to 85 c, v in = 2.8 to 4.5 v, licell = 1.8 to 3.3 v, and typi cal external component values. typical values are characterized at v in = 3.6 v, licell = 3.0 v, and 25 c, unless otherwise noted. parameters symbol min typ max units vcoredig (digital core supply) output voltage on mode (20) coin cell mode and off v coredig ? ? 1.5 1.3 ? ? v vcore (analog core supply) output voltage on mode and charging (20) off and coin cell mode v core ? ? 2.775 0.0 ? ? v vcoreref (bandgap / regulator reference) output voltage (20) v coreref ?1.2?v absolute accuracy v corerefacc ?0.5?% temperature drift v corereftacc ?0.25?% notes 20. 3.0 v < v in < 4.5 v, no external loading on vcoredig, vcore, or vcoreref. extended operation down to uvdet, but no system malfunction. 21. for information only. table 18. external components for core voltages regulator capacitor value ( p f) vcoredig 1.0 vcore 1.0 vcoreref 0.22
vinrefddr vrefddr vinrefddr c half1 discharge + _ vhalf vrefddr c half2 100 nf 100 nf c refddr 1.0 uf analog integrated circuit device data 26 freescale semiconductor pf0100 functional block requi rements and behaviors bias and references block description figure 6. vrefddr block diagram 7.3.2.1 vrefddr control register the vrefddr voltage reference is controlled by a single bit in vrefddcrtl register in table 19 . external components table 19. register vrefddcrtl - addr 0x6a name bit # r/w default description unused 3:0 ? 0x00 unused vrefddren 4 r/w 0x00 enable or disables vrefddr output voltage 0 = vrefddr disabled 1 = vrefddr enabled unused 7:5 ? 0x00 unused table 20. vrefddr external components (22) capacitor capacitance ( f) vinrefddr (23) to vhalf 0.1 vhalf to gnd 0.1 vrefddr 1.0 notes 22. use x5r or x7r capacitors. 23. vinrefddr to gnd, 1.0 f minimum capacitance is provided by buck regulator output.
analog integrated circuit device data freescale semiconductor 27 pf0100 functional block requirements and behaviors bias and references block description vrefddr specifications table 21. vrefddr elec trical characteristics t a = -40 to 85 c, v in = 3.6 v, i refddr = 0.0 ma, v inrefddr = 1.5 v and typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, i refddr = 0.0 ma, v inrefddr = 1.5 v, and 25 c, unless otherwise noted. parameter symbol min typ max unit vrefddr operating input voltage range v inrefddr 1.2 ? 1.8 v operating load current range i refddr 0.0 ? 10 ma current limit i refddr when v refddr is forced to v inrefddr /4 i refddrlim 11.25 15 25 ma quiescent current (24) i refddrq ?8.0? p a active mode ? dc output voltage 1.2 v < v inrefddr < 1.8 v 0.0 ma < i refddr < 10 ma v refddr ?v inrefddr /2 ? v output voltage tolerance 1.2 v < v inrefddr < 1.8 v 0.6 ma d i refddr d 10 ma v refddrtol ?1.0 ? 1.0 % load regulation 1.0 ma < i refddr < 10 ma 1.2 v < v inrefddr < 1.8 v v refddrlor ?0.40?mv/ma active mode ? ac turn-on time enable to 90% of end value v inrefddr = 1.2 v, 1.8 v i refddr = 0.0 ma t onrefddr ? ? 100 p s turn-off time disable to 10% of initial value v inrefddr = 1.2 v, 1.8 v i refddr = 0.0 ma t offrefddr ??10ms start-up overshoot v inrefddr = 1.2 v, 1.8 v i refddr = 0.0 ma v refddrosh ?1.06.0% transient load response v inrefddr = 1.2 v, 1.8 v v refddrtlr ?5.0?mv notes 24. when vrefddr is off there is a quiescent current of 1.5 p a typical.
analog integrated circuit device data 28 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4 power generation 7.4.1 modes of operation the operation of the pf0100 can be reduced to five stat es, or modes: on, off, sleep, standby, and coin cell. figure 7 shows the state diagram of the pf0100, along with the c ond itions to enter and exit from each state. pwron = 0 held >= 4.0 sec any swxomode bits=1 & pwronrsten = 1 (pwron_cfg=1) pwron=1 & vin > uvdet (pwron_cfg =0) or pwron= 0 < 4.0 sec & vin > uvdet (pwron_cfg=1) on pwron = 0 any swxomode bits=1 (pwron_cfg=0) or pwron=0 held >= 4.0 sec any swxomode bits=1 & pwronrsten = 1 (pwron_cfg=1) pwron=1 & vin > uvdet (pwron_cfg = 0) or pwron= 0 < 4.0 sec & vin > uvdet (pwron_cfg=1) pwron = 0 all swxomode bits= 0 (pwron_cfg = 0) or pwron = 0 held >= 4.0 sec all swxomode bits= 0 & pwronrsten = 1 (pwron_cfg = 1) off sleep coin cell vin < uvdet vin > uvdet thermal shudown standby standby asserted vin < uvdet thermal shutdown thermal shutdown standby de-asserted pwron = 0 any swxomode bits=1 (pwron_cfg=0) or pwron=0 held >= 4.0 sec any swxomode bits=1 & pwronrsten = 1 (pwron_cfg=1) pwron = 0 all swxomode bits= 0 (pwron_cfg = 0) or pwron = 0 held >= 4.0 sec all swxomode bits= 0 & pwronrsten = 1 (pwron_cfg = 1) vin < uvdet vin < uvdet figure 7. state diagram to complement the state diagram in figure 7 , a description of the states is provided in following sections. note that v in must exceed the rising uvdet threshold to allow a power up. refer to table 28 for the uvdet thresholds. additionally, i 2 c control is not possible in the coin cell mode and the interrupt signal, intb, is only active in sleep, standby, and on states. 7.4.1.1 on mode the pf0100 enters the on mode after a turn-on event. resetbmcu is de-assert ed, high, in this mode of operation.
analog integrated circuit device data freescale semiconductor 29 pf0100 functional block requirements and behaviors power generation 7.4.1.2 off mode the pf0100 enters the off mode after a turn-off event. a thermal shutdown event also forces the pf0100 into the off mode. only vcoredig and vsnvs are powered in the mode of operation. to exit the off mode, a valid turn-on event is required. resetbmcu is asserted, low, in this mode. 7.4.1.3 standby mode ? depending on standby pin configuration, st andby is entered when the standby pin is asserted. this is typically used for low-power mode of operation. ? when standby is de-asserted, standby mode is exited. a product may be designed to go into a low-power mode after periods of inactivity. the standby pin is provided for board level control of going in and out of such deep sleep modes (dsm). when a product is in dsm, it may be able to reduce the overal l platform current by lowering the regulator output voltage, chang ing the operating mode of the regulators or disabling some regulator s. the configuration of the re gulators in standby is pre- programmed through the i 2 c interface. note that the standby pin is programmable for active high or active low polarity, and that decoding of a standby event will take into account the programmed input polarity as shown in table 22 . when the pf0100 is powered up first, regulator settings for the standby mode are mirrored from the regulator settings for the on mode. to change the standby pin polarity to active low, set the standbyinv bit via software first, and then change the regulator settings for standby mode as required. for simplicity, standby will generally be referred to as active high throughout this document. since standby pin activity is driven asynchronously to the system , a finite time is required for the internal logic to qualify and respond to the pin level changes. a programmable delay is prov ided to hold off the system response to a standby event. this allows the processor and peripherals some time after a standby in struction has been received to terminate processes to facilita te seamless entering into standby mode. when enabled (stbydly = 01, 10, or 11) per table 23 , stbydly will delay the standby init iated response for the entire ic, until the stbydly counter expires. an allowance should be made for three additional 32 k cycles required to synchronize the standby event. table 22. standby pin and polarity control standby (pin) (26) standbyinv (i 2 c bit) (27) standby control (25) 00 0 01 1 10 1 11 0 notes 25. standby = 0: system is not in sta ndby, standby = 1: system is in standby 26. the state of the standby pin only has influence in on mode. 27. bit 6 in power control register (addr - 0x1b) table 23. standby dela y - initiated response stbydly[1:0] (28) function 00 no delay 01 one 32 k period (default) 10 two 32 k periods 11 three 32 k periods notes 28. bits [5:4] in power control register (addr - 0x1b)
analog integrated circuit device data 30 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.1.4 sleep mode ? depending on pwron pin configuration, sleep mode is entered when pwron is de-asserted and swxomode bit is set. ? to exit sleep mode, assert the pwron pin. in the sleep mode, the regulator will use the set point as prog rammed by sw1xoff[5:0] for sw1a /b/c and by swxoff[6:0] for sw2, sw3a/b, and sw4. the activated regulators will maintain settings for this mode and voltage until the next turn-on event. table 24 shows the control bits in sleep mode. during sleep mode, interrupts are active and the intb pin will report any unmasked fault event. 7.4.1.5 coin cell mode in the coin cell state, the coin ce ll is the only valid power source (v in = 0.0 v) to the pmic. no turn-on event is accepted in the coin cell state. transition to the off state requires that v in surpasses uvdet threshold. resetbmcu is held low in this mode. if the coin cell is depl eted, a complete system reset will occur. at t he next application of power and the dete ction of a turn- on event, the system will be re-initialized with all i 2 c bits including, those that reset on coinporb are restored to their default states. table 24. regulator mode control swxomode off operational mode (sleep) (29) 0off 1pfm notes 29. for sleep mode, an activated switching regulator, should use the off mode set point as programmed by sw1xoff[5:0] for sw1a/b/c and swxoff[6:0] for sw2, sw3a/b, and sw4.
analog integrated circuit device data freescale semiconductor 31 pf0100 functional block requirements and behaviors power generation 7.4.2 state machine flow summary table 25 provides a summary matrix of the pf0100 flow diagram to s how the conditions needed to transition from one state to another. 7.4.2.1 turn on events from off and sleep modes, the pmic is powered on by a turn-on event. the type of turn-on event depends on the configuration of pwron. pwron may be configured as an active high when pwron_cfg = 0, or as the input of a mechanical switch when pwron_cfg = 1. v in must be greater than uvdet for t he pmic to turn-on. when pwron is configured as an active high and pwron is high (pulled up to vsnvs) before v in is valid, a v in transition from 0.0 v to a voltage greater than uvdet is also a turn-on event. see the state diagram, figure 7 , and the table 25 for more details. any regulator enabled in the sleep mode will remain enabled when transitioning from sleep to on, i.e., the r egulator will not be turned off and then on again to match the s tart- up sequence. the following is a more detail ed description of the pwron configurations: ? if pwron_cfg = 0, the pwron signal is high and v in > uvdet, the pmic will turn on; the interrupt and sense bits, pwroni and pwrons respectively, will be set. ? if pwron_cfg = 1, v in > uvdet and pwron transitions from high to low, the pmic will turn on; the interrupt and sense bits, pwroni and pwrons respectively, will be set. table 25. state machine flow summary state next state off coin cell sleep standby on initial state off xv in < uvdet x x pwron_cfg = 0 pwron = 1 & v in > uvdet or pwron_cfg = 1 pwron = 0 < 4.0 s & v in > undet coin cell v in > uvdet x x x x sleep thermal shutdown v in < uvdet x x pwron_cfg = 0 pwron = 1 & v in > uvdet or pwron_cfg = 1 pwron = 0 < 4.0 s & v in > undet pwron_cfg = 1 pwron = 0
analog integrated circuit device data 32 freescale semiconductor pf0100 functional block requi rements and behaviors power generation the sense bit will show the real time stat us of the pwron pin. in this configurat ion, the pwron input can be a mechanical switch debounced through a programmable debouncer, pwrondbn c[1:0], to avoid a response to a very short (i.e., unintentional) key press. the in terrupt is generated for both the falling and th e rising edge of the pwro n pin. by default, a 3 0 ms interrupt debounce is applied to both falling and rising edges. the falling edge debounce timing can be extended with pwrondbnc[1:0] as defined in the table bel ow. the interrupt is clear ed by software, or when cycling through the off mode. 7.4.2.2 turn off events pwron pin the pwron pin is used to power off the pf0100. the pwron pin can be configured with otp to power off the pmic under the following two conditions: 1. pwron_cfg bit = 0, swxomode bit = 0 and pwron pin is low. 2. pwron_cfg bit = 1, swxomode bit = 0, pwronrs ten = 1 and pwron is held low for longer than 4.0 seconds. alternatively, t he system can be configured to restart automatically by setting the restarten bit. thermal protection if the die temperature surpasses a given th reshold, the thermal protection circuit wil l power off the pmic to avoid damage. a t urn- on event will not power on the pmic while it is in thermal protection. the part will re main in off mode until the die temperatu re decreases below a given threshold. there are no specific inte rrupts related to this other than the warning interrupt. see power dissipation section for more detailed information. under-voltage detection when the voltage at vin drops below the under-voltage falling th reshold, uvdet, the state machine will transition to the coin cell mode. 7.4.3 power tree the pf0100 pmic features six buck regulators, one boost regula tor, six general purpose ldos , one switch/ldo combination, and a ddr voltage reference to supply voltages for the applicat ion processor and peripheral devices. the buck regulators as well as the boost regulator are supplied directly from the main input supply (v in ). the inputs to all of t he buck regulators must be tied to vin, whether they are pow ered on or off. the six general use ldo regulators are directly supplied from the main input supply or from the switching regulators depending on the application requirements. since vrefddr is intended to provide ddr memory reference voltage, it should be supplied by any ra il supplying voltage to ddr memories; the typical application recommends the use of sw3 as the input s upply for vrefddr. vsnvs is supplied by ei ther the main input supply or the coin cell. refer to table 27 for a summary of all power supplies provided by the pf0100. table 26. pwron hardwa re debounce bit settings bits state turn on debounce (ms) falling edge int debounce (ms) rising edge int debounce (ms) pwrondbnc[1:0] 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 notes 30. the sense bit, pwrons, is not debounced and follows the state of the pwron pin.
analog integrated circuit device data freescale semiconductor 33 pf0100 functional block requirements and behaviors power generation figure 8 shows a simplified power map with various recommended options to supply the different block within the pf0100, as well as the typical application voltage do main on the i.mx6x processor. note that each application power tree is dependent upon the system?s voltage and current require ments, therefore a proper input voltag e should be selected for the regulators. the minimum operating voltage for the main v in supply is 2.8 v, for lower voltages proper operat ion is not guaranteed. however at initial power up, the input voltage must surpass the rising uvdet threshol d before proper operation is guaranteed. refer to the representative tables and text specif ying each supply for information on performance metrics and operating ranges. table 28 summarizes the uvdet thresholds. table 27. power tree summary supply output voltage (v) step size (mv) maximum load current (ma) sw1a/b 0.3 - 1.875 25 2500 sw1c 0.3 - 1.875 25 2000 sw2 0.4 - 3.3 25/50 2000 sw3a/b 0.4 - 3.3 25/50 1250 (31) sw4 0.5*sw3a_out, 0.4 - 3.3 25/50 1000 swbst 5.00/5.05/5.10/5.15 50 600 vgen1 0.80 ? 1.55 50 100 vgen2 0.80 ? 1.55 50 250 vgen3 1.8 ? 3.3 100 100 vgen4 1.8 ? 3.3 100 350 vgen5 1.8 ? 3.3 100 100 vgen6 1.8 ? 3.3 100 200 vsnvs 1.0 - 3.0 na 0.4 vrefddr 0.5*sw3a_out na 10 notes 31. current rating per independent phase, when sw3a/b is set in single or dual phase, current capability is up to 2500 ma. table 28. uvdet threshold uvdet threshold v in rising 3.1 v falling 2.65 v
sw2 vddhigh (0.4 to 3.3 v), 2.0 a vddarm_in vddsoc_in vddhigh_in vdd_ddr_io i.mx6x mcu ldo_3p0 swbst 5.0 v, 0.6 a sw3b ddr io (0.4 to 3.3 v), 1.25 a sw3a ddr core (0.4 to 3.3 v), 1.25 a sw1c soc (0.3 to 1.875 v), 2.0 a sw1b core (0.3 to 1.875 v), 1.25 a sw1a core (0.3 to 1.875 v), 1.25 a usb_otg peripherals vgen1 (0.80 to 1.55 v), 100 ma vgen2 (0.80 to 1.55 v), 250 ma vgen3 (1.8 to 3.3 v), 100 ma vsnvs_in vgen4 (1.8 to 3.3 v), 350 ma vgen5 (1.8 to 3.3 v), 100 ma vgen6 (1.8 to 3.3 v), 200 ma ddr3 sw4 system/vtt (0.4 to 3.3 v) (0.5*vddr) 1.0 a vrefddr 0.5*vddr, 10 ma coincell vin sw3a/b vin sw2 sw4 vin max = 3.4 v vin 2.8 - 4.5 v vin max = 3.6 v vsnvs 1.0 to 3.0 v, 400 ua mux / coin chrg vin max = 4.5 v vin sw2 sw4 vin sw2 sw4 analog integrated circuit device data 34 freescale semiconductor pf0100 functional block requi rements and behaviors power generation figure 8. pf0100 typical power map
analog integrated circuit device data freescale semiconductor 35 pf0100 functional block requirements and behaviors power generation 7.4.4 buck regulators each buck regulator is capable of operating in pfm, aps, and pwm switching modes. 7.4.4.1 current limit each buck regulator has a programmable current limit. in an over-c urrent condition, the current is limited cycle-by-cycle. if t he current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 7.4.4.2 general control to improve system efficiency the buck regulators can operate in different switching modes. ch anging between switching modes can occur by any of the following means: i 2 c programming, exiting/entering the stand by mode, exiting/entering sleep mode, and load current variation. available switchin g modes for buck regulators are presented in table 29 . during soft-start of the buck regulators, the controller trans itions through the pfm, aps, and pwm switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the contro ller transitions to the selected switching mode. depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. table 30 summarizes the buck regulator programmability for normal and standby modes. table 29. switching mode description mode description off the regulator is switched off and the output voltage is discharged. pfm in this mode, the regulator is always in pf m mode, which is useful at light loads for optimized efficiency. pwm in this mode, the regulator is always in pwm mode operation regardles s of load conditions. aps in this mode, the regulator moves autom atically between pulse skipping mode and pwm mode depending on load conditions. table 30. regulator mode control swxmode[3:0] normal mode standby mode 0000 off off 0001 pwm off 0010 reserved reserved 0011 pfm off 0100 aps off 0101 pwm pwm 0110 pwm aps 0111 reserved reserved 1000 aps aps 1001 reserved reserved 1010 reserved reserved 1011 reserved reserved 1100 aps pfm 1101 pwm pfm
analog integrated circuit device data 36 freescale semiconductor pf0100 functional block requi rements and behaviors power generation transitioning between normal and standby modes can affect a change in switching modes as well as output voltage. the rate of the output voltage change is controlled by the dynamic voltage scaling (dvs), explained in dynamic voltage scaling . for each regulator, the output voltage options ar e the same for normal and standby modes. when in standby mode, the regulator outputs the voltage programmed in its standby vo ltage register and will operate in the mode selected by the swxmode[3:0] bits. upon exiting standby mode, the regulator will re turn to its normal switching mode and its output voltage programmed in its voltage register. any regulators whose swxomode bit is set to ?1? will enter sl eep mode if a pwron turn-off event occurs, and any regulator whose swxomode bit is set to ?0? will be turned off. in slee p mode, the regulator outputs the voltage programmed in its off (sleep) voltage register and operates in the pfm mode. the re gulator will exit the sleep mode when a turn-on event occurs. any regulator whose swxomode bit is set to ?1? will remain on and ch ange to its normal configuration settings when exiting the slee p state to the on state. any regulator whose swxomode bit is set to ?0? will be powered up with the same delay in the start-up sequence as when powering on from off. at this point, the regulat or returns to its default on state output voltage and switch mode settings. table 24 shows the control bits in sleep mode. when sleep mode is activated by the sw xomode bit, the regulator will use the set point as programmed by sw1xoff[5:0] for sw1a/b /c and by swxoff[6:0] for sw2, sw3a/b, and sw4. dynamic voltage scaling to reduce overall power consumption, proc essor core voltages can be varied dependi ng on the mode or activity level of the processor. 1. normal operation: the output voltage is selected by i 2 c bits sw1x[5:0] for sw1a/b/c and swx[6:0] for sw2, sw3a/b, and sw4. a voltage transition initiated by i 2 c is governed by the dvs stepping rates shown in table 33 and table 34 . 2. standby mode: the output voltage can be higher, or lower than in normal operati on, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by i 2 c bits sw1xstby[5:0] for sw1a/b/c and by bits swxstby[6:0] for sw2, sw3a/b, and sw4. voltage transi tions initiated by a standby event are governed by the sw1xdvsspeed[1:0] and swxdvsspeed[1:0] i 2 c bits shown in table 33 and table 34 , respectively. 3. sleep mode: the output voltage can be higher or lower than in normal operation, but is typicall y selected to be the lowest state retention voltage of a given processor; it is selected by i 2 c bits sw1xoff[5:0] for sw1a/b/c and by bits swxoff[6:0] for sw2, sw3a/b, and sw4. voltage transitio ns initiated by a turn-off event are governed by the sw1xdvsspeed[1:0] and swxdvsspeed[1:0] i 2 c bits shown in table 33 and table 34 , respectively. table 31 , table 32 , table 33 , and table 34 summarize the set point control and dvs time stepping applied to all regulators. 1110 reserved reserved 1111 reserved reserved table 31. dvs control logic for sw1a/b/c standby set point selected by 0 sw1x[5:0] 1 sw1xstby[5:0] table 32. dvs control logic for sw2, sw3a/b, and sw4 standby set point selected by 0 swx[6:0] 1 swxstby[6:0] table 30. regulator mode control swxmode[3:0] normal mode standby mode
analog integrated circuit device data freescale semiconductor 37 pf0100 functional block requirements and behaviors power generation the regulators have a strong sourcing capability and sinking capability in pwm mode, therefore the fastest rising and falling slopes are determined by the regulator in pwm mode. however, if the regulators are programmed in pf m or aps mode during a dvs transition, the falling slope can be influenced by the lo ad. additionally, as the current capability in pfm mode is reduc ed, controlled dvs transitions in pfm mode coul d be affected. critically timed dvs trans itions are best assured with pwm mode operation. the following diagram shows the general behavior for the regulators when initiated with i 2 c programming, or standby control. during the dvs period the over-current cond ition on the regulator should be masked. actual output voltage example actual output voltage possible output voltage window internally controlled steps output voltage with light load initial set point voltage change request internally controlled steps output voltage requested set point initiated by i2c programming, standby control request for higher voltage request for lower voltage figure 9. voltage stepping with dvs regulator phase clock the swxphase[1:0] bits select the phas e of the regulator clock as shown in table 35 . by default, each regulat or is initialized at 90 out of phase with respect to each other. for example, sw1x is set to 0 , sw2 is set to 90 , sw3a/b is set to 180 , and sw 4 is set to 270 by default at power up. table 33. dvs speed selection for sw1a/b/c sw1xdvsspeed[1:0] function 00 25 mv step each 2.0 s 01 (default) 25 mv step each 4.0 s 10 25 mv step each 8.0 s 11 25 mv step each 16 s table 34. dvs speed selection for sw2, sw3a/b, and sw4 swxdvsspeed[1:0] function swx[6] = 0 or swxstby[6] = 0 function swx[6] = 1 or swxstby[6] = 1 00 25 mv step each 2.0 s 50 mv step each 4.0 s 01 (default) 25 mv step each 4.0 s 50 mv step each 8.0 s 10 25 mv step each 8.0 s 50 mv step each 16 s 11 25 mv step each 16 s 50 mv step each 32 s
analog integrated circuit device data 38 freescale semiconductor pf0100 functional block requi rements and behaviors power generation the swxfreq[1:0] register is used to set the desired switching frequency for each one of the buck regulators. table 37 shows the selectable options for swxfreq[1:0]. for each frequency, all phases will be availabl e, this allows regulators operating at different frequencies to have different relative switching phas es. however, not all combinations are practical. for example, 2.0 mhz, 90 and 4.0 mhz, 180 are the same in terms of phasing. table 36 shows the optimum phasing when using more than one switching frequency. programmable maximum current the maximum current, iswx max , of each buck regulator is programmable. this allows the use of smaller inductors where lower currents are required. programmability is accomplished by choosing the number of para lleled power stages in each regulator. the swx_pwrstg[2:0] bits on the extended page 2 of the register map control the number of power stages. see table 38 for the programmable options. bit[0] must always be enabled to ensure the stage with the current sensor is chosen. the default setting, swx_pwrstg[2:0] = 111, represents the highest maximum current. the current limit for each option is also scaled by the percentage of power stages that are enabled. table 35. regulator phase clock selection swxphase[1:0] phase of clock sent to regulator (degrees) 00 0 01 90 10 180 11 270 table 36. optimum phasing frequencies optimum phasing 1.0 mhz 2.0 mhz 0 180 1.0 mhz 4.0 mhz 0 180 2.0 mhz 4.0 mhz 0 180 1.0 mhz 2.0 mhz 4.0 mhz 0 90 90 table 37. regulator frequency configuration swxfreq[1:0] frequency 00 1.0 mhz 01 2.0 mhz 10 4.0 mhz 11 reserved
analog integrated circuit device data freescale semiconductor 39 pf0100 functional block requirements and behaviors power generation table 38. programmable current configuration regulators control bits % of power stages enabled rated current (a) sw1ab sw1ab_pwrstg[2:0] isw1ab max 0 0 1 40% 1.0 0 1 1 80% 2.0 1 0 1 60% 1.5 1 1 1 100% 2.5 sw1c sw1c_pwrstg[2:0] isw1c max 0 0 1 43% 0.9 0 1 1 58% 1.2 1 0 1 86% 1.7 1 1 1 100% 2.0 sw2 sw2_pwrstg[2:0] isw2 max 0 0 1 38% 0.75 0 1 1 75% 1.5 1 0 1 63% 1.25 1 1 1 100% 2.0 sw3a sw3a_pwrstg[2:0] isw3a max 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 sw3b sw3b_pwrstg[2:0] isw3b max 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 sw4 sw4_pwrstg[2:0] isw4 max 0 0 1 50% 0.5 0 1 1 75% 0.75 1 0 1 75% 0.75 1 1 1 100% 1.0
analog integrated circuit device data 40 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.4.3 sw1a/b/c sw1/a/b/c are 2.5 to 4.5 a buck regulators that can be configured in va rious phasing schemes, depending on the desired cost/ performance trade-offs. the followin g configurations are available: ? sw1a/b/c single phase with one inductor ? sw1a/b as a single phase with one inductor and sw1c in independent mode with one inductor ? sw1a/b as a dual phase with two inductors and sw1c in independent mode with one inductor the desired configuration is progr ammed by otp by using sw1_config[1:0] bits in the register map extended page 1 , as shown in table 39 . . table 39. sw1 configuration sw1_config[1:0] description 00 a/b/c single phase 01 a/b single phase c independent mode 10 a/b dual phase c independent mode 11 reserved
analog integrated circuit device data freescale semiconductor 41 pf0100 functional block requirements and behaviors power generation sw1a/b/c single phase in this configuration, all phases a, b, and c, are connected together to a si ngle inductor, thus, providing up to 4.50 a current capa bility for high current applications. the feedback and all ot her controls are accomplished by use of pin sw1cfb and sw1c control registers, respectively. figure 10 shows the connection for sw1a/b/c in single phase mode. during single phase mode operation, all three phases will use the same configuration for frequency, phase, and dvs speed set in sw1cconf register. however, the same configuration se ttings for frequency, phase, and dvs speed setting on sw1ab registers should be used. the sw1fb pin shou ld be left floating in this configuration. driver controller sw1ain sw1alx sw1fb i sense c osw1a c insw1a l sw1 i2c interface gndsw1a sw1a/b/c sw1amode sw1afault vin driver controller sw1bin sw1blx i sense c insw1b gndsw1b sw1bmode sw1bfault vin ea z1 z2 internal compensation v ref dac i2c driver controller ea z1 z2 internal compensation sw1cin sw1clx sw1cfb i sense c insw1c gndsw1c sw1cmode sw1cfault v ref dac i2c vin figure 10. sw1a/b/c single phase block diagram
analog integrated circuit device data 42 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw1a/b single phase - sw1c independent mode in this configuration, sw1a/b is connected as a single ph ase with a single inductor, while sw1c is used as an independent output, using its own inductor and configurations parameters. this configuration allows reduced component count by using only one inductor for sw1a/b. as mentioned before, sw1a/b and sw1c operate independently from one another, thus, they can be operated with a different voltage set point for normal, standby, an d sleep modes, as well as switching mode selection and on/ off control. figure 11 shows the physical connection for sw1a/b in single phase and sw1c as an independent output. driver controller sw1ain sw1alx sw1fb i sense c osw1a c insw1a l sw1a i2c interface gndsw1a sw1a/b sw1amode sw1afault vin driver controller sw1bin sw1blx i sense c insw1b gndsw1b sw1bmode sw1bfault vin ea z1 z2 internal compensation v ref dac i2c driver controller ea z1 z2 internal compensation sw1cin sw1clx sw1cfb i sense c osw1c c insw1c l sw1c gndsw1c sw1c sw1cmode sw1cfault v ref dac i2c vin figure 11. sw1a/b single phase, sw1c independent mode block diagram both sw1alx and sw1blx nodes operate at the same dvs, frequ ency, and phase configured by the sw1abconf register, while sw1clx node operates independently, using the configuration in the sw1cconf register.
analog integrated circuit device data freescale semiconductor 43 pf0100 functional block requirements and behaviors power generation sw1a/b dual phase - sw 1c independent mode in this mode, sw1a/b is connected in dual phase mode using one inductor per switching node, while sw1c is used as an independent output using its own inductor and configuration paramet ers. this mode provides a smaller output voltage ripple on the sw1a/b output. as menti oned before, sw1a/b and sw1c operate independently from one another, thus, they can be operated with a different voltage set point for normal, standby, an d sleep modes, as well as switching mode selection and on/ off control. figure 12 shows the physical connection for sw1a/b in dual phase and sw1c as an independent output. vin driver controller ea z1 z2 internal compensation sw1ain sw1alx sw1fb i sense c osw1a c insw1a l sw1a i2c interface gndsw1a sw1ab sw1amode sw1afault v ref dac i2c driver controller sw1bin sw1blx i sense c osw1b c insw1b l sw1b gndsw1b sw1bmode sw1bfault vin driver controller ea z1 z2 internal compensation sw1cin sw1clx sw1cfb i sense c osw1c c insw1c l sw1c gndsw1c sw1c sw1cmode sw1cfault v ref dac i2c vin figure 12. sw1a/b dual phase, sw1c independent mode block diagram in this mode of operation, sw1alx and sw 1bl x nodes operate automatically at 180 phase shift from each other and use the same freq uency and dvs configured by sw1abconf regi ster, while sw1clx node operate independently using the configuration in the sw1cconf register.
analog integrated circuit device data 44 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw1a/b/c setup and control registers sw1a/b and sw1c output voltages are programmable from 0.300 to 1.875 v in steps of 25 mv. the output voltage set point is independently programmed for normal, standby, and sleep mode by setting the sw1x [5:0], sw1xstby[5:0], and sw1xoff[5:0] bits respectively. table 40 shows the output voltage coding for sw1a/b or sw1c. table 40. sw1a/b/c output voltage configuration set point sw1x[5:0] sw1xstby[5:0] sw1xoff[5:0] sw1x output (v) set point sw1x[5:0] sw1xstby[5:0] sw1xoff[5:0] sw1x output (v) 0 000000 0.3000 32 100000 1.1000 1 000001 0.3250 33 100001 1.1250 2 000010 0.3500 34 100010 1.1500 3 000011 0.3750 35 100011 1.1750 4 000100 0.4000 36 100100 1.2000 5 000101 0.4250 37 100101 1.2250 6 000110 0.4500 38 100110 1.2500 7 000111 0.4750 39 100111 1.2750 8 001000 0.5000 40 101000 1.3000 9 001001 0.5250 41 101001 1.3250 10 001010 0.5500 42 101010 1.3500 11 001011 0.5750 43 101011 1.3750 12 001100 0.6000 44 101100 1.4000 13 001101 0.6250 45 101101 1.4250 14 001110 0.6500 46 101110 1.4500 15 001111 0.6750 47 101111 1.4750 16 010000 0.7000 48 110000 1.5000 17 010001 0.7250 49 110001 1.5250 18 010010 0.7500 50 110010 1.5500 19 010011 0.7750 51 110011 1.5750 20 010100 0.8000 52 110100 1.6000 21 010101 0.8250 53 110101 1.6250 22 010110 0.8500 54 110110 1.6500 23 010111 0.8750 55 110111 1.6750 24 011000 0.9000 56 111000 1.7000 25 011001 0.9250 57 111001 1.7250 26 011010 0.9500 58 111010 1.7500 27 011011 0.9750 59 111011 1.7750 28 011100 1.0000 60 111100 1.8000 29 011101 1.0250 61 111101 1.8250 30 011110 1.0500 62 111110 1.8500 31 011111 1.0750 63 111111 1.8750
analog integrated circuit device data freescale semiconductor 45 pf0100 functional block requirements and behaviors power generation table 41 provides a list of registers used to configure and operat e sw1a/b/c and a detailed description on each one of these register is provided in table 42 through table 51 . table 41. sw1a/b/c register summary register address output sw1abvolt 0x20 sw1ab output voltage set point in normal operation sw1abstby 0x21 sw1ab output voltage set point on standby sw1aboff 0x22 sw1ab output voltage set point on sleep sw1abmode 0x23 sw1ab switching mode selector register sw1abconf 0x24 sw1ab dvs, phase, frequency and ilim configuration sw1cvolt 0x2e sw1c output voltage set point in normal operation sw1cstby 0x2f sw1c output voltage set point in standby sw1coff 0x30 sw1c output voltage set point in sleep sw1cmode 0x31 sw1c switching mode selector register sw1cconf 0x32 sw1c dvs, phase, frequency and ilim configuration table 42. register sw1abvolt - addr 0x20 name bit # r/w default description sw1ab 5:0 r/w 0x00 sets the sw1ab output voltage during normal operation mode. see table 40 for all possible configurations. unused 7:6 ? 0x00 unused table 43. register sw1abstby - addr 0x21 name bit # r/w default description sw1abstby 5:0 r/w 0x00 sets the sw1ab output voltage during standby mode. see table 40 for all possible configurations. unused 7:6 ? 0x00 unused table 44. register sw1aboff - addr 0x22 name bit # r/w default description sw1aboff 5:0 r/w 0x00 sets the sw1ab output voltage during sleep mode. see table 40 for all possible configurations. unused 7:6 ? 0x00 unused
analog integrated circuit device data 46 freescale semiconductor pf0100 functional block requi rements and behaviors power generation table 45. register sw1abmode - addr 0x23 name bit # r/w default description sw1abmode 3:0 r/w 0x80 sets the sw1ab switching operation mode. see table 30 for all possible configurations. unused 4 ? 0x00 unused sw1abomode 5 r/w 0x00 set status of sw1ab when in sleep mode 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 46. register sw1abconf - addr 0x24 name bit # r/w default description sw1abilim 0 r/w 0x00 sw1ab current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw1abfreq 3:2 r/w 0x00 sw1a/b switching frequency selector. see table 37 . sw1abphase 5:4 r/w 0x00 sw1a/b phase clock selection. see table 35 . sw1abdvsspeed 7:6 r/w 0x00 sw1a/b dvs speed selection. see table 33 . table 47. register sw1cvolt - addr 0x2e name bit # r/w default description sw1c 5:0 r/w 0x00 sets the sw1c output voltage during normal operation mode. see table 40 for all possible configurations. unused 7:6 ? 0x00 unused table 48. register sw1cstby - addr 0x2f name bit # r/w default description sw1cstby 5:0 r/w 0x00 sets the sw1c output voltage during standby mode. see table 40 for all possible configurations. unused 7:6 ? 0x00 unused table 49. register sw1coff - addr 0x30 name bit # r/w default description sw1coff 5:0 r/w 0x00 sets the sw1c output voltage during sleep mode. see table 40 for all possible configurations. unused 7:6 ? 0x00 unused
analog integrated circuit device data freescale semiconductor 47 pf0100 functional block requirements and behaviors power generation sw1a/b/c external components table 50. register sw1cmode - addr 0x31 name bit # r/w default description sw1cmode 3:0 r/w 0x80 sets the sw1c switching operation mode. see table 29 for all possible configurations. unused 4 ? 0x00 unused sw1comode 5 r/w 0x00 set status of sw1c when in sleep mode 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 51. register sw1cconf - addr 0x32 name bit # r/w default description sw1cilim 0 r/w 0x00 sw1c current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw1cfreq 3:2 r/w 0x00 sw1c switching frequency selector. see table 37 . sw1cphase 5:4 r/w 0x00 sw1c phase clock selection. see table 35 . sw1cdvsspeed 7:6 r/w 0x00 sw1c dvs speed selection. see table 33 . table 52. sw1a/b/c external component recommendations mode components description a/b/c single phase a/b single - c independent mode a/b dual - c independent mode c insw1a (32) sw1a input capacitor 4.7 p f4.7 p f4.7 p f c in1ahf (32) sw1a decoupling input capacitor 0.1 p f0.1 p f0.1 p f c insw1b (32) sw1b input capacitor 4.7 p f4.7 p f4.7 p f c in1bhf (32) sw1b decoupling input capacitor 0.1 p f0.1 p f0.1 p f c insw1c (32) sw1c input capacitor 4.7 p f4.7 p f4.7 p f c in1chf (32) sw1c decoupling input capacitor 0.1 p f0.1 p f0.1 p f c osw1ab (32) sw1a/b output capacitor 6 x 22 p f4 x 22 p f 4 x 22 p f c osw1c (32) sw1c output capacitor ? 2 x 22 p f 2 x 22 p f l sw1a sw1a inductor 1.0 p h dcr = 12 m : i sat = 4.5 a 1.0 p h dcr = 12 m : i sat = 4.5 a 1.0 p h dcr = 60 m : i sat = 2.4 a l sw1b sw1b inductor ? ? 1.0 p h dcr = 60 m : i sat = 2.4 a
analog integrated circuit device data 48 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw1a/b/c specifications l sw1c sw1c inductor ? 1.0 p h dcr = 60 m : i sat = 2.4 a 1.0 p h dcr = 60 m : i sat = 2.4 a notes 32. use x5r or x7r capacitors. table 53. sw1a/b/c el ectrical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], typical external component values, f sw1x = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit sw1a/b/c (single phase) operating input voltage vin sw1a vin sw1b vin sw1c 2.8 ? 4.5 v nominal output voltage v sw1abc ? table 40 ?v output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw1abc < 4.5 a 0.3 v d v sw1abc d 1.450 v 1.475 v d v sw1abc d 1.875 v ? pfm, steady state, 2.8 v < v in < 4.5 v, 0 < i sw1abc < 150 ma 0.3 v < v sw1abc < 0.85 v 0.875 v < v sw1abc < 1.875 v v sw1abcacc -25 -3.0% -65 -6.0% ? ? ? ? 25 3.0% 65 6.0% mv % rated output load current, 2.8 v < v in < 4.5 v, 0.3 v < v sw1abc < 1.875 v i sw1abc ? ? 4500 ma current limiter peak current detection ? current through inductor sw1abilim = 0 sw1abilim = 1 i sw1abclim 7.1 5.3 10.5 7.9 13.7 10.3 a start-up overshoot i sw1abc = 0 ma dvs clk = 25 mv/4 p s, v in = vin sw1x = 4.5 v, v sw1abc = 1.875 v v sw1abcosh ??66mv turn-on time enable to 90% of end value i sw1x = 0 ma dvs clk = 25 mv/4.0 p s, v in = vin sw1x = 4.5 v, v sw1abc = 1.875 v ton sw1abc ? ? 500 s switching frequency sw1xfreq[1:0] = 00 sw1xfreq[1:0] = 01 sw1xfreq[1:0] = 10 f sw1abc ? ? ? 1.0 2.0 4.0 ? ? ? mhz table 52. sw1a/b/c external component recommendations mode components description a/b/c single phase a/b single - c independent mode a/b dual - c independent mode
analog integrated circuit device data freescale semiconductor 49 pf0100 functional block requirements and behaviors power generation sw1a/b/c (single phase) (continued) efficiency ?v in = 3.6 v, f sw1abc = 2.0 mhz, l sw1abc = 1.0 p h pfm, 0.9 v, 1.0 ma pfm, 1.2 v, 50 ma aps, pwm, 1.2 v, 850 ma aps, pwm, 1.2 v, 1275 ma aps, pwm, 1.2 v, 2125 ma aps, pwm, 1.2 v, 4500 ma k sw1abc ? ? ? ? ? ? 77 82 86 84 80 68 ? ? ? ? ? ? % output ripple ' v sw1abc ?10?mv line regulation (aps, pwm) v sw1abclir ??20mv dc load regulation (aps, pwm) v sw1abclor ??20mv transient load regulation ? transient load = 0 to 2.25 a, di/dt = 100 ma/ p s overshoot undershoot v sw1abclotr ? ? ? ? 50 50 mv quiescent current pfm mode aps mode i sw1abcq ? ? 18 145 ? ? a discharge resistance r sw1abcdis ? 600 ? : sw1a/b (single/dual phase) operating input voltage vin sw1a vin sw1b 2.8 ? 4.5 v nominal output voltage v sw1ab ? table 40 ?v output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw1ab < 2.5 a 0.3 v d v sw1ab d 1.450 v 1.475 v d v sw1ab d 1.875 v ? pfm, steady state, 2.8 v < v in < 4.5 v, 0 < i sw1ab < 150 ma 0.3 v < v sw1ab < 0.85 v 0.875 v < v sw1ab < 1.875 v v sw1abacc -25 -3.0% -65 -6.0% - - ? ? 25 3.0% 65 6.0% mv % rated output load current, (34) 2.8 v < v in < 4.5 v, 0.3 v < v sw1ab < 1.875 v i sw1ab ? ? 2500 ma current limiter peak current detection (34) ? sw1a/b single phase (current through inductor) sw1abilim = 0 sw1abilim = 1 ? sw1a/b dual phase (current through inductor per phase) sw1abilim = 0 sw1abilim = 1 i sw1ablim 4.5 3.3 2.2 1.6 6.5 4.9 3.2 2.4 8.5 6.4 4.3 3.2 a start-up overshoot i sw1ab = 0.0 ma dvs clk = 25 mv/4 p s, v in = vin sw1x = 4.5 v, v sw1ab = 1.875 v v sw1abosh ??66mv table 53. sw1a/b/c el ectrical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], typical external component values, f sw1x = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 50 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw1a/b (single/dual phase) (continued) turn-on time enable to 90% of end value i sw1ab = 0.0 ma dvs clk = 25 mv/4 p s, v in = vin sw1x = 4.5 v, v sw1ab = 1.875 v ton sw1ab ? ? 500 s switching frequency sw1abfreq[1:0] = 00 sw1abfreq[1:0] = 01 sw1abfreq[1:0] = 10 f sw1ab ? ? ? 1.0 2.0 4.0 ? ? ? mhz efficiency (single phase) ?v in = 3.6 v, f sw1ab = 2.0 mhz, l sw1ab = 1.0 p h pfm, 0.9 v, 1.0 ma pfm, 1.2 v, 50 ma aps, pwm, 1.2 v, 500 ma aps, pwm, 1.2 v, 750 ma aps, pwm, 1.2 v, 1250 ma aps, pwm, 1.2 v, 2500 ma k sw1ab ? ? ? ? ? ? 82 84 86 87 82 71 ? ? ? ? ? ? % output ripple ' v sw1ab ?10?mv line regulation (aps, pwm) v sw1ablir ??20mv dc load regulation (aps, pwm) v sw1ablor ??20mv transient load regulation ? transient load = 0 to 1.25 a, di/dt = 100 ma/ p s overshoot undershoot v sw1ablotr ? ? ? ? 50 50 mv quiescent current pfm mode aps mode i sw1abq ? ? 18 235 ? ? a sw1a p-mosfet r dson vin sw1a = 3.3 v r onsw1ap ? 215 245 m : sw1a n-mosfet r dson vin sw1a = 3.3 v r onsw1an ? 258 326 m : sw1a p-mosfet leakage current vin sw1a = 4.5 v i sw1apq ??7.5a sw1a n-mosfet leakage current vin sw1a = 4.5 v i sw1anq ??2.5a sw1b p-mosfet r dson vin sw1b = 3.3 v r onsw1bp ? 215 245 m : sw1b n-mosfet r dson vin sw1b = 3.3 v r onsw1bn ? 258 326 m : sw1b p-mosfet leakage current vin sw1b = 4.5 v i sw1bpq ??7.5a sw1b n-mosfet leakage current vin sw1b = 4.5 v i sw1bnq ??2.5a discharge resistance r sw1abdis ? 600 ? : table 53. sw1a/b/c el ectrical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], typical external component values, f sw1x = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data freescale semiconductor 51 pf0100 functional block requirements and behaviors power generation sw1c (independent) operating input voltage vin sw1c 2.8 ? 4.5 v nominal output voltage v sw1c ? table 40 ?v output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw1c < 2.0 a 0.3 v d v sw1c d 1.450 v 1.475 v d v sw1c d 1.875 v ? pfm, steady state 2.8 v < v in < 4.5 v, 0 < i sw1c < 50 ma 0.3 v < v sw1c < 0.85 v 0.875 v < v sw1c < 1.875 v v sw1cacc -25 -3.0% -65 -6.0% ? ? ? ? 25 3.0% 65 6.0% mv rated output load current 2.8 v < v in < 4.5 v, 0.3 v < v sw1c < 1.875 v i sw1c ? ? 2000 ma current limiter peak current detection ? current through inductor sw1cilim = 0 sw1cilim = 1 i sw1clim 2.6 (33) 1.95 4.0 3.0 5.2 3.9 a start-up overshoot i sw1c = 0 ma dvs clk = 25 mv/4 p s, v in = vin sw1c = 4.5 v, v sw1c = 1.875 v v sw1cosh ??66mv turn-on time enable to 90% of end value i sw1c = 0 ma dvs clk = 25 mv/4 p s, v in = vin sw1c = 4.5 v, v sw1c = 1.875 v ton sw1c ? ? 500 s switching frequency sw1cfreq[1:0] = 00 sw1cfreq[1:0] = 01 sw1cfreq[1:0] = 10 f sw1c ? ? ? 1.0 2.0 4.0 ? ? ? mhz efficiency ?v in = 3.6 v, f sw1c = 2.0 mhz, l sw1c = 1.0 p h pfm, 0.9 v, 1.0 ma pfm, 1.2 v, 50 ma aps, pwm, 1.2 v, 400 ma aps, pwm, 1.2 v, 600 ma aps, pwm, 1.2 v, 1000 ma aps, pwm, 1.2 v, 2000 ma k sw1c ? ? ? ? ? ? 77 78 86 84 78 65 ? ? ? ? ? ? % output ripple ' v sw1c ?10?mv line regulation (aps, pwm) v sw1clir ??20mv dc load regulation (aps, pwm) v sw1clor ??20mv transient load regulation ? transient load = 0.0 ma to 1.0 a, di/dt = 100 ma/ p s overshoot undershoot v sw1clotr ? ? ? ? 50 50 mv quiescent current pfm mode aps mode i sw1cq ? ? 22 145 ? ? a table 53. sw1a/b/c el ectrical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], typical external component values, f sw1x = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 52 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw1c (independent) (continued) sw1c p-mosfet r dson at vin sw1c = 3.3 v r onsw1cp ? 184 206 m : sw1c n-mosfet r dson at vin sw1c = 3.3 v r onsw1cn ? 211 260 m : sw1c p-mosfet leakage current vin sw1c = 4.5 v i sw1cpq ??10.5a sw1c n-mosfet leakage current vin sw1c = 4.5 v i sw1cnq ??3.5a discharge resistance r sw1cdis ? 600 ? : notes 33. meets 1.89 a current rating for vddsoc_in domain on i.mx6x processor. 34. current rating of sw1ab supports the power virus mode of operation of the i.mx6x processor. table 53. sw1a/b/c el ectrical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], typical external component values, f sw1x = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1x = 1.2 v, i sw1x = 100 ma, sw1x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit
0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ? ( % ) load ? current ? (ma) pfm ?\ vout ? = ? 1.2v aps ?\ vout ? = ? 1.2v pwm ?\ vout ? = ? 1.2v efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 e f f i c i e n c y ? ( % ) load ? current ? (ma) pfm ?\ vout ? = ? 1.2v aps ?\ vout ? = ? 1.2v pwm ?\ vout ? = ? 1.2v efficiency (%) sw1ab single phase sw1c independent mode 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 10000 e f f i c i e n c y ? ( % ) load ? current(ma) pfm \ vout=1.2v aps \ vout=1.2v pwm \ vout=1.2v efficiency (%) sw1abc single phase analog integrated circuit device data freescale semiconductor 53 pf0100 functional block requirements and behaviors power generation figure 13. sw1ab and sw1c efficiency waveforms
analog integrated circuit device data 54 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.4.4 sw2 sw2 is a single phase, 2.0 a rated buck regulator. table 29 describes the modes, and table 30 show the options for the swxmode[3:0] bits. figure 14 shows the block diagram and the external component connections for sw2 regulator. driver controller ea z1 z2 internal compensation sw2in sw2lx sw2fb i sense c osw2 c insw2 l sw2 i2c interface gndsw2 sw2 sw2mode sw2fault v ref dac i2c vin figure 14. sw2 block diagram sw2 setup and c ontrol registers sw2 output voltage is programmable from 0.400 to 3.300 v; however, bit sw2[6] in regist er sw2volt is read-only during normal operation. its value is determined by the default configur ation, or may be changed by using the otp registers. therefore , once sw2[6] is set to ?0?, the output will be limited to the lower output voltages from 0.400 to 1.975 v with 25 mv increments, as determine d by bits sw2[5:0]. likewise, once bit sw2[6] is set to ?1?, the output volt age will be limited to the higher output v oltage range from 0.800 to 3.300 v with 50 mv increments, as determi n ed by bits sw2[5:0]. in order to optimize the performance of th e regulator, it is recommended t hat only voltages fr om 2.000 to 3.300 v be used in the hig h range, and the lower range be used for voltages from 0.400 to 1.975 v. the output voltage set point is independently programmed for no rmal, standby, and sleep mode by setting the sw2[5:0], sw2stby[5:0] and sw2off[5:0] bits , respectively. however, the init ial state of bit sw2[ 6] will be copied into bits sw2stby[6], and sw2off[6] bits. therefore, the output voltage range will remain the same in all three operating modes. table 54 shows the output voltage coding valid for sw2. table 54. sw2 output voltage configuration low output voltage range (35) high output voltage range set point sw2[6:0] sw2 output set point sw2[6:0] sw2 output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000
analog integrated circuit device data freescale semiconductor 55 pf0100 functional block requirements and behaviors power generation 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 table 54. sw2 output voltage configuration low output voltage range (35) high output voltage range set point sw2[6:0] sw2 output set point sw2[6:0] sw2 output
analog integrated circuit device data 56 freescale semiconductor pf0100 functional block requi rements and behaviors power generation setup and control of sw2 is done through i 2 c registers listed in table 55 , and a detailed description of each one of the registers is provided in tables 56 to table 60 . 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 reserved 52 0110100 1.7000 116 1110100 reserved 53 0110101 1.7250 117 1110101 reserved 54 0110110 1.7500 118 1110110 reserved 55 0110111 1.7750 119 1110111 reserved 56 0111000 1.8000 120 1111000 reserved 57 0111001 1.8250 121 1111001 reserved 58 0111010 1.8500 122 1111010 reserved 59 0111011 1.8750 123 1111011 reserved 60 0111100 1.9000 124 1111100 reserved 61 0111101 1.9250 125 1111101 reserved 62 0111110 1.9500 126 1111110 reserved 63 0111111 1.9750 127 1111111 reserved notes 35. for voltages less than 2.0 v, only use set points 0 to 63. table 55. sw2 register summary register address description sw2volt 0x35 output voltage set point on normal operation sw2stby 0x36 output voltage set point on standby sw2off 0x37 output voltage set point on sleep sw2mode 0x38 switching mode selector register sw2conf 0x39 dvs, phase, frequency, and ilim configuration table 56. register sw2volt - addr 0x35 name bit # r/w default description sw2 5:0 r/w 0x00 sets the sw2 output voltage during normal operation mode. see table 54 for all possible configurations. sw2 6 r 0x00 sets the operating output voltage range for sw2. set during otp or tbb configuration only. see table 54 for all possible configurations. unused 7 ? 0x00 unused table 54. sw2 output voltage configuration low output voltage range (35) high output voltage range set point sw2[6:0] sw2 output set point sw2[6:0] sw2 output
analog integrated circuit device data freescale semiconductor 57 pf0100 functional block requirements and behaviors power generation table 57. register sw2stby - addr 0x36 name bit # r/w default description sw2stby 5:0 r/w 0x00 sets the sw2 output voltage during standby mode. see table 54 for all possible configurations. sw2stby 6 r 0x00 sets the operating output voltage range for sw2 on standby mode. this bit inherits the value configured on bit sw2[6] during otp or tbb configuration. see table 54 for all possible configurations. unused 7 ? 0x00 unused table 58. register sw2off - addr 0x37 name bit # r/w default description sw2off 5:0 r/w 0x00 sets the sw2 output voltage during sleep mode. see table 54 for all possible configurations. sw2off 6 r 0x00 sets the operating output voltage range for sw2 on sleep mode. this bit inherits the value configured on bit sw2[6] during otp or tbb configuration. see table 54 for all possible configurations. unused 7 ? 0x00 unused table 59. register sw2mode - addr 0x38 name bit # r/w default description sw2mode 3:0 r/w 0x80 sets the sw2 switching operation mode. see table 29 for all possible configurations. unused 4 ? 0x00 unused sw2omode 5 r/w 0x00 set status of sw2 when in sleep mode 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 60. register sw2conf - addr 0x39 name bit # r/w default description sw2ilim 0 r/w 0x00 sw2 current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw2freq 3:2 r/w 0x00 sw2 switching frequency selector. see table 37 . sw2phase 5:4 r/w 0x00 sw2 phase clock selection. see table 35 . sw2dvsspeed 7:6 r/w 0x00 sw2 dvs speed selection. see table 34 .
analog integrated circuit device data 58 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw2 external components sw2 specifications table 61. sw2 external component recommendations components description values c insw2 (36) sw2 input capacitor 4.7 p f c in2hf (36) sw2 decoupling input capacitor 0.1 p f c osw2 (36) sw2 output capacitor 2 x 22 p f l sw2 sw2 inductor 1.0 p h dcr = 50 m : i sat = 2.65 a notes 36. use x5r or x7r capacitors. table 62. sw2 electr ical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], typica l external component values, f sw2 = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit switch mode supply sw2 operating input voltage (37) vin sw2 2.8 ? 4.5 v nominal output voltage v sw2 ? table 54 ?v output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw2 < 2.0 a 0.4 v < v sw2 < 0.85 v 0.875 v < v sw2 < 1.975 v 2.0 v < v sw2 < 3.3 v ? pfm, 2.8 v < v in < 4.5 v, 0 < i sw2 d 50 ma 0.4 v < v sw2 < 0.85 v 0.875 v < v sw2 < 1.975 v 2.0 v < v sw2 < 3.3 v v sw2acc -25 -3.0% -6.0% -65 -6.0% -6.0% ? ? ? ? ? ? 25 3.0% 6.0% 65 6.0% 6.0% mv % rated output load current (38) 2.8 v < v in < 4.5 v, 0.4 v < v sw2 < 3.3 v i sw2 ? ? 2000 ma current limiter peak current detection ? current through inductor sw2ilim = 0 sw2ilim = 1 i sw2lim 2.8 2.1 4.0 3.0 5.2 3.9 a start-up overshoot i sw2 = 0.0 ma dvs clk = 25 mv/4 p s, v in = vin sw2 = 4.5 v v sw2osh ??66mv turn-on time enable to 90% of end value i sw2 = 0.0 ma dvs clk = 50 mv/8 p s, v in = vin sw2 = 4.5 v ton sw2 ? ? 550 s switching frequency sw2freq[1:0] = 00 sw2freq[1:0] = 01 sw2freq[1:0] = 10 f sw2 ? ? ? 1.0 2.0 4.0 ? ? ? mhz
analog integrated circuit device data freescale semiconductor 59 pf0100 functional block requirements and behaviors power generation switch mode supply sw2 (continued) efficiency ?v in = 3.6 v, f sw2 = 2.0 mhz, l sw2 = 1.0 p h pfm, 3.15 v, 1.0 ma pfm, 3.15 v, 50 ma aps, pwm, 3.15 v, 400 ma aps, pwm, 3.15 v, 600 ma aps, pwm, 3.15 v, 1000 ma aps, pwm, 3.15 v, 2000 ma k sw2 ? ? ? ? ? ? 94 95 96 94 92 86 ? ? ? ? ? ? % output ripple ' v sw2 ?10?mv line regulation (aps, pwm) v sw2lir ??20mv dc load regulation (aps, pwm) v sw2lor ??20mv transient load regulation ? transient load = 0.0 ma to 1.0 a, di/dt = 100 ma/ p s overshoot undershoot v sw2lotr ? ? ? ? 50 50 mv quiescent current pfm mode aps mode (low output voltage settings) aps mode (high output voltage settings) i sw2q ? ? ? 23 145 305 ? ? ? a sw2 p-mosfet r dson at v in = vin sw2 = 3.3 v r onsw2p ? 190 209 m : sw2 n-mosfet r dson at v in = vin sw2 = 3.3 v r onsw2n ? 212 255 m : sw2 p-mosfet leakage current v in = vin sw2 = 4.5 v i sw2pq ??12a sw2 n-mosfet leakage current v in = vin sw2 = 4.5 v i sw2nq ??4.0a discharge resistance r sw2dis ? 600 ? : notes 37. when output is set to > 2.6 v the output will follow the input down when v in gets near 2.8 v. 38. the higher output voltages available depend on the voltage dr op in the conduction path as give n by the following equation: (vin sw2 - v sw2 ) = i sw2 * (dcr of inductor +r onsw2p + pcb trace resistance). table 62. sw2 electr ical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], typica l external component values, f sw2 = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. parameter symbol min typ max unit
0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ? ( % ) load ? current ? (ma) pfm ?\ vout ? = ? 3.15v aps ?\ vout ? = ? 3.15v pwm ?\ vout ? = ? 3.15v efficiency (%) analog integrated circuit device data 60 freescale semiconductor pf0100 functional block requi rements and behaviors power generation figure 15. sw2 efficiency waveforms 7.4.4.5 sw3a/b sw3a/b are 1.25 to 2.5 a rated buck regulators, depending on the configuration. table 29 describes the available switching modes and table 30 show the actual configuration options for the sw3xmode[3:0] bits. sw3a/b can be configured in various phasing schemes, depending on th e desired cost/perform ance trade-offs. the following configurations are available: ? a single phase ? a dual phase ? independent regulators the desired configuration is programmed in otp by using the sw3_config[1:0] bits. table 63 shows the options for the sw3cfg[1:0] bits. table 63. sw3 configuration sw3_config[1:0] description 00 a/b single phase 01 a/b single phase 10 a/b dual phase 11 a/b independent
analog integrated circuit device data freescale semiconductor 61 pf0100 functional block requirements and behaviors power generation sw3a/b single phase in this configuration, sw3alx and sw3blx are connect ed in single phase with a single inductor a shown in figure 16 , this configuration reduces cost and component count. feedback is taken from the sw3afb pin and the sw3bfb pin must be left open. although control is from sw3a, registers of both regulators, sw3a and sw3b, must be identically set. driver controller sw3ain sw3alx sw3afb i sense c osw3a c insw3a l sw3a i2c interface gndsw3a sw3 sw3amode sw3afault vin driver controller sw3bin sw3blx i sense c insw3b gndsw3b sw3bmode sw3bfault vin ea z1 z2 internal compensation v ref dac i2c ea z1 z2 internal compensation v ref dac i2c sw3bfb figure 16. sw3a/b single phase block diagram
analog integrated circuit device data 62 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw3a/b dual phase sw3a/b can be connected in dual p hase configuration using one inductor per switching node, as shown in figure 17 . this mode allows a smaller output voltage ripple. fee dba ck is taken from pin sw3afb and pin sw 3bfb must be left ope n. although control is from sw3a, registers of both regulators, sw3a and sw3b, must be identically set. in this configuration, the regulators switc h 180 degrees apart. driver controller ea z1 z2 internal compensation sw3ain sw3alx sw3afb i sense c osw3a c insw3a l sw3a i2c interface gndsw3a sw3 sw3amode sw3afault v ref dac i2c vin driver controller sw3bin sw3blx i sense c osw3b c insw3b l sw3b gndsw3b sw3bmode sw3bfault vin ea z1 z2 internal compensation v ref dac i2c sw3bfb figure 17. sw3a/b dual phase block diagram
analog integrated circuit device data freescale semiconductor 63 pf0100 functional block requirements and behaviors power generation sw3a - sw3b independent outputs sw3a and sw3b can be configured as independent outputs as shown in figure 18 , providing flexibility for applications requiring more voltage rails with less current cap abi lity. each output is configured and cont rolled independently by its respective i 2 c registers as shown in table 65 . driver controller ea z1 z2 internal compensation sw3ain sw3alx sw3afb i sense c osw3a c insw3a l sw3a i2c interface gndsw3a sw3a sw3amode sw3afault v ref dac i2c vin driver controller ea z1 z2 internal compensation sw3bin sw3blx sw3bfb i sense c osw3b c insw3b l sw3b gndsw3b sw3b sw3bmode sw3bfault v ref dac i2c vin figure 18. sw3a/b independent output block diagram sw3a/b setup and control registers sw3a/b output voltage is progr ammable from 0.400 to 3.300 v; however, bit sw3x[6] in regist er sw3xvolt is read-only during normal operation. its value is determined by the default configur ation, or may be changed by using the otp registers. therefore , once sw3x[6] is set to ?0?, the output will be limit ed to the lower output voltages from 0.40 to 1.975 v with 25 mv increments, as determine d by bits sw3x[5:0]. likewise, once bit sw3x[6] is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 v with 50 mv increments, as determined by bits sw3x[5:0]. in order to optimize the performance of the regulator, i t is recommended that only voltages from 2.00 to 3.300 v be used in the hig h range and that that the lower ran ge be used for voltages from 0.400 to 1.975 v. the output voltage set point is independently programmed for no rma l, standby, and sleep mode by setting the sw3x[5:0], sw3xstby[5:0], and sw3xoff[5:0] bits respectively; however, the initial state of the sw3x[6] bit will be copied into the sw3xstby[6] and sw3xoff[6] bits. therefore, th e output voltage range will remain th e same on all three operating modes. table 64 shows the output voltage coding valid for sw3x.
analog integrated circuit device data 64 freescale semiconductor pf0100 functional block requi rements and behaviors power generation table 64. sw3a/b output voltage configuration low output voltage range (39) high output voltage range set point sw3x[6:0] sw3x output set point sw3x[6:0] sw3xoutput 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500
analog integrated circuit device data freescale semiconductor 65 pf0100 functional block requirements and behaviors power generation 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 reserved 52 0110100 1.7000 116 1110100 reserved 53 0110101 1.7250 117 1110101 reserved 54 0110110 1.7500 118 1110110 reserved 55 0110111 1.7750 119 1110111 reserved 56 0111000 1.8000 120 1111000 reserved 57 0111001 1.8250 121 1111001 reserved 58 0111010 1.8500 122 1111010 reserved 59 0111011 1.8750 123 1111011 reserved 60 0111100 1.9000 124 1111100 reserved 61 0111101 1.9250 125 1111101 reserved 62 0111110 1.9500 126 1111110 reserved 63 0111111 1.9750 127 1111111 reserved notes 39. for voltages less than 2.0 v, only use set points 0 to 63. table 64. sw3a/b output voltage configuration low output voltage range (39) high output voltage range set point sw3x[6:0] sw3x output set point sw3x[6:0] sw3xoutput
analog integrated circuit device data 66 freescale semiconductor pf0100 functional block requi rements and behaviors power generation table 65 provides a list of registers used to configure and operate sw3a/b. a detailed description on each of these register is provided on tables 66 through table 75 . table 65. sw3ab register summary register address output sw3avolt 0x3c sw3a output voltage set point on normal operation sw3astby 0x3d sw3a output voltage set point on standby sw3aoff 0x3e sw3a output voltage set point on sleep sw3amode 0x3f sw3a switching mode selector register sw3aconf 0x40 sw3a dvs, phase, frequency and ilim configuration sw3bvolt 0x43 sw3b output voltage set point on normal operation sw3bstby 0x44 sw3b output voltage set point on standby sw3boff 0x45 sw3b output voltage set point on sleep sw3bmode 0x46 sw3b switching mode selector register sw3bconf 0x47 sw3b dvs, phase, frequency and ilim configuration table 66. register sw3avolt - addr 0x3c name bit # r/w default description sw3a 5:0 r/w 0x00 sets the sw3a output voltage (independent) or sw3a/b output voltage (single/dual phase), during normal operation mode. see table 64 for all possible configurations. sw3a 6 r 0x00 sets the operating output voltage range for sw3a (independent) or sw3a/b (single/dual phase). set during otp or tbb configuration only. see table 64 for all possible configurations. unused 7 ? 0x00 unused table 67. register sw3astby - addr 0x3d name bit # r/w default description sw3astby 5:0 r/w 0x00 sets the sw3a output voltage (independent) or sw3a/b output voltage (single/dual phase), during standby mode. see table 64 for all possible configurations. sw3astby 6 r 0x00 sets the operating output voltage range for sw3a (independent) or sw3a/b (single/dual phase) on standby mode. this bit inherits the value configured on bit sw3a[6] during otp or tbb configuration. see table 64 for all possible configurations. unused 7 ? 0x00 unused
analog integrated circuit device data freescale semiconductor 67 pf0100 functional block requirements and behaviors power generation table 68. register sw3aoff - addr 0x3e name bit # r/w default description sw3aoff 5:0 r/w 0x00 sets the sw3a output voltage (independent) or sw3a/b output voltage (single/dual phase), during sleep mode. see table 64 for all possible configurations. sw3aoff 6 r 0x00 sets the operating output voltage range for sw3a (independent) or sw3a/b (single/dual phase) on sleep mode. this bit inherits the value configured on bit sw3a[6] during otp or tbb configuration. see table 64 for all possible configurations. unused 7 ? 0x00 unused table 69. register sw3amode - addr 0x3f name bit # r/w default description sw3amode 3:0 r/w 0x80 sets the sw3a (independent) or sw3a/b (single/dual phase) switching operation mode. see table 29 for all possible configurations. unused 4 ? 0x00 unused sw3aomode 5 r/w 0x00 set status of sw3a (independent) or sw3a/b (single/dual phase) when in sleep mode. 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 70. register sw3aconf - addr 0x40 name bit # r/w default description sw3ailim 0 r/w 0x00 sw3a current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw3afreq 3:2 r/w 0x00 sw3a switching frequency selector. see table 37 . sw3aphase 5:4 r/w 0x00 sw3a phase clock selection. see table 35 . sw3advsspeed 7:6 r/w 0x00 sw3a dvs speed selection. see table 34 . table 71. register sw3bvolt - addr 0x43 name bit # r/w default description sw3b 5:0 r/w 0x00 sets the sw3b output voltage (independent) during normal operation mode. see table 64 for all possible configurations. sw3b 6 r 0x00 sets the operating output voltage range for sw3b (independent). set during otp or tbb configuration only. see table 64 for all possible configurations. unused 7 ? 0x00 unused
analog integrated circuit device data 68 freescale semiconductor pf0100 functional block requi rements and behaviors power generation table 72. register sw3bstby - addr 0x44 name bit # r/w default description sw3bstby 5:0 r/w 0x00 sets the sw3b output voltage (independent) during standby mode. see table 64 for all possible configurations. sw3bstby 6 r 0x00 sets the operating output voltage range for sw3b (independent) on standby mode. this bit inherits the value configured on bit sw3b[6] during otp or tbb configuration. see table 64 for all possible configurations. unused 7 ? 0x00 unused table 73. register sw3boff - addr 0x45 name bit # r/w default description sw3boff 5:0 r/w 0x00 sets the sw3b output voltage (independent) during sleep mode. see table 64 for all possible configurations. sw3boff 6 r 0x00 sets the operating output voltage range for sw3b (independent) on sleep mode. this bit inherits the value configured on bit sw3b[6] during otp or tbb configuration. see table 64 for all possible configurations. unused 7 ? 0x00 unused table 74. register sw3bmode - addr 0x46 name bit # r/w default description sw3bmode 3:0 r/w 0x80 sets the sw3b (independent) switching operation mode. see table 29 for all possible configurations. unused 4 ? 0x00 unused sw3bomode 5 r/w 0x00 set status of sw3b (independent) when in sleep mode. 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 75. register sw3bconf - addr 0x47 name bit # r/w default description sw3bilim 0 r/w 0x00 sw3b current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw3bfreq 3:2 r/w 0x00 sw3b switching frequency selector. see table 37 . sw3bphase 5:4 r/w 0x00 sw3b phase clock selection. see table 35 . sw3bdvsspeed 7:6 r/w 0x00 sw3b dvs speed selection. see table 34 .
analog integrated circuit device data freescale semiconductor 69 pf0100 functional block requirements and behaviors power generation sw3a/b external components sw3a/b specifications table 76. sw3a/b external component requirements mode components description sw3a/b single phase sw3a/b dual phase sw3a independent sw3b independent c insw3a (40) sw3a input capacitor 4.7 p f4.7 p f4.7 p f c in3ahf (40) sw3a decoupling input capacitor 0.1 p f0.1 p f0.1 p f c insw3b (40) sw3b input capacitor 4.7 p f4.7 p f4.7 p f c in3bhf (40) sw3b decoupling input capacitor 0.1 p f0.1 p f0.1 p f c osw3a (40) sw3a output capacitor 4 x 22 p f 2 x 22 p f 2 x 22 p f c osw3b (40) sw3b output capacitor ? 2 x 22 p f 2 x 22 p f l sw3a sw3a inductor 1.0 p h dcr = 50 m : i sat = 3.9 a 1.0 p h dcr = 60 m : i sat = 3.0 a 1.0 p h dcr = 60 m : i sat = 3.0 a l sw3b sw3b inductor ? 1.0 p h dcr = 60 m : i sat = 3.0 a 1.0 p h dcr = 60 m : i sat = 3.0 a notes 40. use x5r or x7r capacitors. table 77. sw3a/b elec trical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], typical external component values, f sw3x = 2.0 mhz, single/dual phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. p arameter symbol min typ max unit switch mode supply sw3a/b operating input voltage (41) vin sw3x 2.8 ? 4.5 v nominal output voltage v sw3x - table 64 -v output voltage accuracy ? pwm, aps 2.8 v < v in < 4.5 v, 0 < i sw3x < isw3x max 0.4 v < v sw3x < 0.85 v 0.875 v < v sw3x < 1.975 v 2.0 v < v sw3x < 3.3 v ? pfm , steady state (2.8 v < v in < 4.5 v, 0 < i sw3x < 50 ma) 0.4 v < v sw3x < 0.85 v 0.875 v < v sw3x < 1.975 v 2.0 v < v sw3x < 3.3 v v sw3xacc -25 -3.0% -6.0% -65 -6.0% -6.0% ? ? ? ? ? ? 25 3.0% 6.0% 65 6.0% 6.0% mv % rated output load current (42) ? 2.8 v < v in < 4.5 v, 0.4 v < v sw3x < 3.3 v pwm, aps mode single/dual phase pwm, aps mode independent (per phase) i sw3x ? ? ? ? 2500 1250 ma
analog integrated circuit device data 70 freescale semiconductor pf0100 functional block requi rements and behaviors power generation switch mode supply sw3a/b (continued) current limiter peak current detection ? single phase (current through inductor) sw3xilim = 0 sw3xilim = 1 ? independent mode or dual phase (current through inductor per phase) sw3xilim = 0 sw3xilim = 1 i sw3xlim 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 a start-up overshoot i sw3x = 0.0 ma dvs clk = 25 mv/4 p s, v in = vin sw3x = 4.5 v v sw3xosh ??66mv turn-on time enable to 90% of end value i sw3x = 0 ma dvs clk = 25 mv/4 p s, v in = vin sw3x = 4.5 v ton sw3x ? ? 500 s switching frequency sw3xfreq[1:0] = 00 sw3xfreq[1:0] = 01 sw3xfreq[1:0] = 10 f sw3x ? ? ? 1.0 2.0 4.0 ? ? ? mhz efficiency (single phase) ?f sw3 = 2.0 mhz, l sw3x 1.0 p h pfm, 1.5 v, 1.0 ma pfm, 1.5 v, 50 ma aps, pwm 1.5 v, 500 ma aps, pwm 1.5 v, 750 ma aps, pwm 1.5 v, 1250 ma aps, pwm 1.5 v, 2500 ma k sw3ab ? ? ? ? ? ? 84 85 85 84 80 74 ? ? ? ? ? ? % output ripple ' v sw3x ?10?mv line regulation (aps, pwm) v sw3xlir ??20mv dc load regulation (aps, pwm) v sw3xlor ??20mv transient load regulation ? transient load = 0.0 ma to i sw3x /2, di/dt = 100 ma/ p s overshoot undershoot v sw3xlotr ? ? ? ? 50 50 mv quiescent current pfm mode (single/dual phase) aps mode (single/dual phase) pfm mode (independent mode) aps mode (sw3a independent mode) aps mode (sw3b independent mode) i sw3xq ? ? ? ? ? 22 300 50 250 150 ? ? ? ? ? a sw3a p-mosfet r dson at v in = vin sw3a = 3.3 v r onsw3ap ? 215 245 m : sw3a n-mosfet r dson at v in = vin sw3a = 3.3 v r onsw3an ? 258 326 m : sw3a p-mosfet leakage current v in = vin sw3a = 4.5 v i sw3apq ??7.5a table 77. sw3a/b elec trical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], typical external component values, f sw3x = 2.0 mhz, single/dual phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. p arameter symbol min typ max unit
0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ? ( % ) load ? current ? (ma) pfm ?\ vout ? = ? 1.5v aps ?\ vout ? = ? 1.5v pwm ?\ vout ? = ? 1.5v efficiency (%) analog integrated circuit device data freescale semiconductor 71 pf0100 functional block requirements and behaviors power generation figure 19. sw3ab single phase efficiency waveforms 7.4.4.6 sw4 sw4 is a 1.0 a rated single phase buck regulator capable of operating in tw o modes. in its default mode, it operates as a normal buck regulator with a programmabl e output between 0.400 and 3.300 v. it is capable of operating in th e three available switching modes: pfm, aps, and pwm, described on table 29 and configured by the sw4m ode[3:0] bits, as shown in table 30 . if the system requires ddr memory termination, sw4 can be used in its vtt mode. in the vtt mode, its reference voltage will track the output voltage of sw3a, scaled by 0.5. furthermore, when in vtt mode, only the pwm switching mode is allowed. the vtt mode can be configured by use of v tt bit in the otp_sw4_config register. figure 20 shows the block diagram and the external co mponent connections for the sw4 regulator. switch mode supply sw3a/b (continued) sw3a n-mosfet leakage current v in = vin sw3a = 4.5 v i sw3anq ??2 . 5 a sw3b p-mosfet r dson at v in = vin sw3b = 3.3 v r onsw3bp ? 215 245 m : sw3b n-mosfet r dson at v in = vin sw3b = 3.3 v r onsw3bn ? 258 326 m : sw3b p-mosfet leakage current v in = vin sw3b = 4.5 v i sw3bpq ??7 . 5 a sw3b n-mosfet leakage current v in = vin sw3b = 4.5 v i sw3bpq ??2 . 5 a discharge resistance r sw3xdis ? 600 ? : notes 41. when output is set to > 2.6 v the output will follow the input down when v in gets near 2.8 v. 42. the higher output voltages available depend on the voltage dr op in the conduction path as give n by the following equation: (vin sw3x - v sw3x ) = i sw3x * (dcr of inductor +r onsw3xp + pcb trace resistance). table 77. sw3a/b elec trical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], typical external component values, f sw3x = 2.0 mhz, single/dual phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. p arameter symbol min typ max unit
driver controller ea z1 z2 internal compensation sw4in sw4lx sw4fb i sense c osw4 c insw4 l sw4 i2c interface gndsw4 sw4 sw4mode sw4fault v ref dac i2c vin analog integrated circuit device data 72 freescale semiconductor pf0100 functional block requi rements and behaviors power generation figure 20. sw4 block diagram sw4 setup and c ontrol registers to set the sw4 in regulator or vtt mode, bit vtt of the register ot p_sw4_conf register on extended page 1 , is programmed during otp or tbb configuration; setting bit vtt to ?1? will enable sw 4 to operate in vtt mode and ?0? in regulator mode. see one time programmability (otp) for detailed information on otp configuration. in regulator mode, the sw4 output voltage is prog rammable from 0.400 to 3.300 v; however, bit sw4[6] in the sw4volt register is read-o nly during normal operati on. its value is determined by the default c onfiguration, or may be changed by using the otp registers. once sw 4[6] is set to ?0?, the output will be limited to the lower output voltage s, from 0.400 to 1.975 v with 25 mv increments, as determined by th e sw4[5:0] bits. likewise, once the sw4[6] bit is set to "1", the output voltage will be limited to the higher output volt age range from 0.800 to 3.300 v with 50 mv increments, as determined by the sw4[5:0] bits. in order to optimize the performance of th e regulator, it is recommended t hat only voltages fr om 2.000 to 3.300 v be used in the hig h range and that that the lower ran ge be used for voltages from 0.400 to 1.975 v. the output voltage set point is independently programmed for no rmal, standby, and sleep mode by setting the sw4[5:0], sw4stby[5:0], and sw4off[5:0] bits, respec tively. however, the initial state of the sw4[6] bit will be copied into bits sw4stby[6], and sw4off[6] bits, so the output voltage ran ge will remain the same on all three operating modes. table 78 shows the output voltage coding valid for sw4. table 78. sw4 output voltage configuration low output voltage range (43) high output voltage range set point sw4[6:0] sw4 output set point sw4[6:0] sw4 output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000
analog integrated circuit device data freescale semiconductor 73 pf0100 functional block requirements and behaviors power generation 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 table 78. sw4 output voltage configuration low output voltage range (43) high output voltage range set point sw4[6:0] sw4 output set point sw4[6:0] sw4 output
analog integrated circuit device data 74 freescale semiconductor pf0100 functional block requi rements and behaviors power generation full setup and control of sw4 is done through the i 2 c registers listed on table 79 , and a detailed description of each one of the registers is provided in tables 80 to table 84 . 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 reserved 52 0110100 1.7000 116 1110100 reserved 53 0110101 1.7250 117 1110101 reserved 54 0110110 1.7500 118 1110110 reserved 55 0110111 1.7750 119 1110111 reserved 56 0111000 1.8000 120 1111000 reserved 57 0111001 1.8250 121 1111001 reserved 58 0111010 1.8500 122 1111010 reserved 59 0111011 1.8750 123 1111011 reserved 60 0111100 1.9000 124 1111100 reserved 61 0111101 1.9250 125 1111101 reserved 62 0111110 1.9500 126 1111110 reserved 63 0111111 1.9750 127 1111111 reserved notes 43. for voltages less than 2.0 v, only use set points 0 to 63. table 79. sw4 register summary register address description sw4volt 0x4a output voltage set point on normal operation sw4stby 0x4b output voltage set point on standby sw4off 0x4c output voltage set point on sleep sw4mode 0x4d switching mode selector register sw4conf 0x4e dvs, phase, frequency and ilim configuration table 80. register sw4volt - addr 0x4a name bit # r/w default description sw4 5:0 r/w 0x00 sets the sw4 output voltage during normal operation mode. see table 78 for all possible configurations. sw4 6 r 0x00 sets the operating output voltage range for sw4. set during otp or tbb configuration only. see table 78 for all possible configurations. unused 7 ? 0x00 unused table 78. sw4 output voltage configuration low output voltage range (43) high output voltage range set point sw4[6:0] sw4 output set point sw4[6:0] sw4 output
analog integrated circuit device data freescale semiconductor 75 pf0100 functional block requirements and behaviors power generation table 81. register sw4stby - addr 0x4b name bit # r/w default description sw4stby 5:0 r/w 0x00 sets the sw4 output voltage during standby mode. see table 78 for all possible configurations. sw4stby 6 r 0x00 sets the operating output voltage range for sw4 on standby mode. this bit inherits the value configured on bit sw4[6] during otp or tbb configuration. see table 78 for all possible configurations. unused 7 ? 0x00 unused table 82. register sw4off - addr 0x4c name bit # r/w default description sw4off 5:0 r/w 0x00 sets the sw4 output voltage during sleep mode. see table 78 for all possible configurations. sw4off 6 r 0x00 sets the operating output voltage range for sw4 on sleep mode. this bit inherits the value configured on bit sw4[6] during otp or tbb configuration. see table 78 for all possible configurations. unused 7 ? 0x00 unused table 83. register sw4mode - addr 0x4d name bit # r/w default description sw4mode 3:0 r/w 0x80 sets the sw4 switching operation mode. see table 29 for all possible configurations. unused 4 ? 0x00 unused sw4omode 5 r/w 0x00 set status of sw4 when in sleep mode 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 84. register sw4conf - addr 0x4e name bit # r/w default description sw4ilim 0 r/w 0x00 sw4 current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw4freq 3:2 r/w 0x00 sw4 switching frequency selector. see table 37 . sw4phase 5:4 r/w 0x00 sw4 phas e clock selection. see table 35 . sw4dvsspeed 7:6 r/w 0x00 sw4 dvs speed selection. see table 34 .
analog integrated circuit device data 76 freescale semiconductor pf0100 functional block requi rements and behaviors power generation sw4 external components sw4 specifications table 85. sw4 external component requirements components description values c insw4 (44) sw4 input capacitor 4.7 p f c in4hf (44) sw4 decoupling input capacitor 0.1 p f c osw4 (44) sw4 output capacitor 2 x 22 p f l sw4 sw4 inductor 1.0 p h dcr = 60 m : i sat = 3.0 a notes 44. use x5r or x7r capacitors. table 86. sw4 electr ical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw4 = 3.6 v, v sw4 = 1.8 v, i sw4 = 100 ma, sw4_pwrstg[2:0] = [101], typica l external component values, f sw4 = 2.0 mhz, single/dual phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw4 = 3.6 v, v sw4 = 1.8 v, i sw4 = 100 ma, sw4_pwrstg[2:0] = [101], and 25 c, unless otherwise noted. parameter symbol min typ max unit switch mode supply sw4 operating input voltage (45) vin sw4 2.8 ? 4.5 v nominal output voltage normal operation vtt mode v sw4 ? ? table 78 v sw3afb /2 ? ? v output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw4 < 1.0 a 0.4 v < v sw4 < 0.85 v 0.875 v < v sw4 < 1.975 v 2.0 v < v sw4 < 3.3 v ? pfm, steady state, 2.8 v < v in < 4.5 v, 0 < i sw4 < 50 ma 0.4 v < v sw4 < 0.85 v 0.875 v < v sw4 < 1.975 v 2.0 v < v sw4 < 3.3 v ? vtt mode , 2.8 v < v in < 4.5 v, 0 < i sw4 < 1.0 a v sw4acc -25 -3.0% -6.0% -65 -6.0% -6.0% -40 ? ? ? ? ? ? ? 25 3.0% 6.0% 65 6.0% 6.0% 40 mv % rated output load current (46) 2.8 v < v in < 4.5 v, 0.4 v < v sw4 < 3.3 v i sw4 ? ? 1000 ma current limiter peak current detection current through inductor sw4ilim = 0 sw4ilim = 1 i sw4lim 1.4 1.0 2.0 1.5 3.0 2.4 a start-up overshoot i sw4 = 0.0 ma dvs clk = 25 mv/4 p s, v in = vin sw4 = 4.5 v v sw4osh ??66mv turn-on time enable to 90% of end value i sw4 = 0.0 ma dvs clk = 25 mv/4 p s, v in = vin sw4 = 4.5 v ton sw4 ? ? 500 s
analog integrated circuit device data freescale semiconductor 77 pf0100 functional block requirements and behaviors power generation switch mode supply sw4 (continued) switching frequency sw4freq[1:0] = 00 sw4freq[1:0] = 01 sw4freq[1:0] = 10 f sw4 ? ? ? 1.0 2.0 4.0 ? ? ? mhz efficiency ?f sw4 = 2.0 mhz, l sw4 = 1.0 p h pfm, 1.8 v, 1.0 ma pfm, 1.8 v, 50 ma aps, pwm 1.8 v, 200 ma aps, pwm 1.8 v, 500 ma aps, pwm 1.8 v, 1000 ma pwm 0.75 v, 200 ma pwm 0.75 v, 500 ma pwm 0.75 v, 1000 ma k sw4 ? ? ? ? ? ? ? ? 81 78 87 88 83 78 76 66 ? ? ? ? ? ? ? ? % output ripple ' v sw4 ?10?mv line regulation (aps, pwm) v sw4lir ??20mv dc load regulation (aps, pwm) v sw4lor ??20mv transient load regulation ? transient load = 0.0 ma to 500 ma, di/dt = 100 ma/ p s overshoot undershoot v sw4lotr ? ? ? ? 50 50 mv quiescent current pfm mode aps mode i sw4q ? ? 22 145 ? ? a sw4 p-mosfet r dson at v in = vin sw4 = 3.3 v r onsw4p ? 236 274 m : sw4 n-mosfet r dson at v in = vin sw4 = 3.3 v r onsw4n ? 293 378 m : sw4 p-mosfet leakage current v in = vin sw4 = 4.5 v i sw4pq ??6.0a sw4 n-mosfet leakage current v in = vin sw4 = 4.5 v i sw4nq ??2.0a discharge resistance r sw4dis ? 600 ? : notes 45. when output is set to > 2.6 v the output will follow the input down when v in gets near 2.8 v. 46. the higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (vin sw4 - v sw4 ) = i sw4 * (dcr of inductor +r onsw4p + pcb trace resistance). table 86. sw4 electrical characteristics all parameters are specified at t a = -40 to 85 c, v in = vin sw4 = 3.6 v, v sw4 = 1.8 v, i sw4 = 100 ma, sw4_pwrstg[2:0] = [101], typical external component values, f sw4 = 2.0 mhz, single/dual phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw4 = 3.6 v, v sw4 = 1.8 v, i sw4 = 100 ma, sw4_pwrstg[2:0] = [101], and 25 c, unless otherwise noted. parameter symbol min typ max unit
0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ? ( % ) load ? current ? (ma) pfm ?\ vout ? = ? 1.8v aps ?\ vout ? = ? 1.8v pwm ?\ vout ? = ? 1.8v pwm ?\ vout ? = ? 0.75v efficiency (%) analog integrated circuit device data 78 freescale semiconductor pf0100 functional block requi rements and behaviors power generation figure 21. sw4 efficiency waveforms
analog integrated circuit device data freescale semiconductor 79 pf0100 functional block requirements and behaviors power generation 7.4.5 boost regulator swbst is a boost regulator with a pr ogrammable output from 5.0 to 5.15 v. swbst can supply the vusb regulator for the usb phy in otg mode, as well as the vbus vo ltage. note that the parasitic leakage path for a boost regulator will cause the swbstout and swbstfb voltage to be a schottky drop below t he input voltage whenever swbst is disabled. the switching nmos transistor is integrated on-chip. figure 22 shows the block diagram and component connection for the boost regulator. swbstlx v obst driver controller ea z1 z2 internal compensation i 2 c interface swbstmode v refuv v ref gndswbst vin l bst c inbst d bst swbstfb r sense sc v refsc swbstfault oc uv c oswbst swbstin figure 22. boost regulator architecture 7.4.5.1 swbst setup and control boost regulator control is done through a single register swbstctl described in table 87 . swbst is included in the power-up sequence if its otp power-up timing bits, swbst_seq[4:0], are not all zeros. table 87. register swbstctl - addr 0x66 name bit # r/w default description swbst1volt 1:0 r/w 0x00 set the output voltage for swbst 00 = 5.000 v 01 = 5.050 v 10 = 5.100 v 11 = 5.150 v swbst1mode 3:2 r 0x02 set the switching mode on normal operation 00 = off 01 = pfm 10 = auto (default) (47) 11 = aps unused 4 ? 0x00 unused swbst1stbymode 6:5 r/w 0x02 set the switching mode on standby 00 = off 01 = pfm 10 = auto (default) (47) 11 = aps
analog integrated circuit device data 80 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.5.2 swbst external components 7.4.5.3 swbst specifications unused 7 ? 0x00 unused notes 47. in auto mode, the controller automatically switches between pfm and aps modes depending on the load current. table 88. swbst external component requirements components description values c inbst (48) swbst input capacitor 10 p f c inbsthf (48) swbst decoupling input capacitor 0.1 p f c obst (48) swbst output capacitor 2 x 22 p f l sbst swbst inductor 2.2 p h d bst swbst boost diode 1.0 a, 20 v schottky notes 48. use x5r or x7r capacitors. table 89. swbst elec trical specifications all parameters are specified at t a = -40 to 85 c, v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, typical external component values, f swbst = 2.0 mhz, otherwise noted. typica l values are characterized at v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, and 25 c, unless otherwise noted. parameters symbol min typ max units switch mode supply swbst input voltage range vin swbst 2.8 ? 4.5 v nominal output voltage v swbst ? table 87 ?v output voltage accuracy 2.8 v d v in d 4.5 v 0 < i swbst < iswbst max v swbstacc -4.0 ? 3.0 % output ripple 2.8 v d v in d 4.5 v 0 < i swbst < iswbst max , excluding reverse recovery of schottky diode ' v swbst ? ? 120 mv vp-p dc load regulation 0 < i swbst < iswbst max v swbstlor ?0.5 ? mv/ ma dc line regulation 2.8 v d v in d 4.5 v, i swbst = iswbst max v swbstlir ? 50 ? mv continuous load current 2.8 v d v in d 3.0 v 3.0 v d v in d 4.5 v i swbst ? ? ? ? 500 600 ma quiescent current auto i swbstq ? 222 289 p a mosfet on resistance r dsonbst ? 206 306 m : peak current limit (49) i swbstlim 1400 2200 3200 ma table 87. register swbstctl - addr 0x66 name bit # r/w default description
analog integrated circuit device data freescale semiconductor 81 pf0100 functional block requirements and behaviors power generation start-up overshoot i swbst = 0.0 ma v swbstosh ? ? 500 mv transient load response i swbst from 1.0 to 100 ma in 1.0 s maximum transient amplitude v swbsttr ? ? 300 mv transient load response i swbst from 100 to 1.0 ma in 1.0 s maximum transient amplitude v swbsttr ? ? 300 mv switch mode supply swbst (continued) transient load response i swbst from 1.0 to 100 ma in 1.0 s time to settle 80% of transient t swbsttr ? ? 500 s transient load response i swbst from 100 to 1.0 ma in 1.0 s time to settle 80% of transient t swbsttr ??20ms nmos off leakage swbstin = 4.5 v, swbstmode [1:0] = 00 i swbsthsq ?1.05.0a turn-on time enable to 90% of v swbst, i swbst = 0.0 ma ton swbst ??2.0ms switching frequency f swbst ?2.0?mhz efficiency i swbst = iswbst max k swbst ?86?% notes 49. only in auto mode. table 89. swbst elec trical specifications all parameters are specified at t a = -40 to 85 c, v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, typical external component values, f swbst = 2.0 mhz, otherwise noted. typica l values are characterized at v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, and 25 c, unless otherwise noted. parameters symbol min typ max units
analog integrated circuit device data 82 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.6 ldo regulators description this section describes the ldo regulators provided by the pf0 100. all regulators use the main bandgap as reference. refer to bias and references block description section for further information on the internal reference voltages. a low power mode is automatically activated by reducing bias curre nts when the load current is less than i_lmax/5. however, the lowest bias currents may be attained by forcing the part into its low power mode by setting the vgenxlpwr bit. the use of this bit is only recommended when the load is expected to be less than i_lmax/50, otherwise performance may be degraded. when a regulator is disabled, the output will be discharged by an internal pull-down. the pull-down is also activated when resetbmcu is low. vgenx vinx vinx vgenx c genx vgenxen vgenxlpwr v ref vgenx i 2 c interface discharge + _ figure 23. general ldo block diagram
analog integrated circuit device data freescale semiconductor 83 pf0100 functional block requirements and behaviors power generation 7.4.6.1 transient response waveforms idealized stimulus and response waveforms for transient line and transient load tests are depicted in figure 25 . note that the transient line and load response refers to the over shoot, or undershoot onl y, excluding the dc shift. figure 24. transient waveforms 10 us 10 us v inx transient line stimulus v inx_initial v inx_final 1.0 us 1.0 us i max /10 i max i load transient load stimulus undershoot i l = i max /10 v out v out transient load response i l = i max overshoot undershoot v out v out transient line response overshoot v inx_initial v inx_final
analog integrated circuit device data 84 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.6.2 short-circuit protection all general purpose ldos have short-circui t protection capability. the short-circ uit protection (scp) system includes debounced fault condition detection, regulator shutdown, and processor interru pt generation, to contain fail ures and minimize the chance of product damage. if a short-circuit condition is detected, the ldo will be disabled by resetting its vgenxen bit, while at the s ame time, an interrupt vgenxfaulti will be generated to flag the fault to the system processor. the vgenxfaulti interrupt is maskable through the vgenxfaultm mask bit. the scp feature is enabled by setting the regscpen bit. if this bit is not set, the regulators will not automatically be disab led upon a short-circuit detection. however, the current limiter will continue to limit the output cu rrent of the regulator. by def ault, the regscpen is not set; therefore, at start- up none of the regulators will be disabled if an overloaded condition occurs. a fault interrupt, vgenxfaulti, will be generated in an overload condi tion regardless of the state of the regscpen bit. see table 90 for scp behavior configuration. 7.4.6.3 ldo regulator control each ldo is fully contro lled through its respective vgenxctl register. this register enables the user to set the ldo output voltage according to table 91 for vgen1 and vgen2; and uses the voltage set point on table 92 for vgen3 through vgen6. table 90. short-circuit behavior regscpen[0] short-circuit behavior 0 current limit 1 shutdown table 91. vgen1, vgen2 ou tput voltage configuration set point vgenx[3:0] vgenx output (v) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550
analog integrated circuit device data freescale semiconductor 85 pf0100 functional block requirements and behaviors power generation besides the output voltage configuration, th e ldos can be enabled or disabled at anyti me during normal mode operation, as well as programmed to stay ?on? or be disabled when the pm ic enters standby mode. each regulator has associated i 2 c bits for this. table 93 presents a summary of all valid combinations of the cont rol bits on vgenxctl register and the expected behavior of the ldo output. table 92. vgen3/ 4/ 5/ 6 output voltage configuration set point vgenx[3:0] vgenx output (v) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 table 93. ldo control vgenxen vgenxlpwr vgenxstby standby (50) vgenxout 0xxxoff 10 0xon 1 1 0 x low power 1x 10on 10 11off 1 1 1 1 low power notes 50. standby refers to a standby event as described earlier.
analog integrated circuit device data 86 freescale semiconductor pf0100 functional block requi rements and behaviors power generation for more detail information, table 94 through table 99 provide a description of all registers necessary to operate all six general purpose ldo regulators. table 94. register vgen1ctl - addr 0x6c name bit # r/w default description vgen1 3:0 r/w 0x80 sets vgen1 output voltage. see table 91 for all possible configurations. vgen1en 4 ? 0x00 enables or disables vgen1 output 0 = off 1 = on vgen1stby 5 r/w 0x00 set vgen1 output state when in standby. refer to table 93 . vgen1lpwr 6 r/w 0x00 enable low power mode for vgen1. refer to table 93 . unused 7 ? 0x00 unused table 95. register vgen2ctl - addr 0x6d name bit # r/w default description vgen2 3:0 r/w 0x80 sets vgen2 output voltage. see table 91 for all possible configurations. vgen2en 4 ? 0x00 enables or disables vgen2 output 0 = off 1 = on vgen2stby 5 r/w 0x00 set vgen2 output state when in standby. refer to table 93 . vgen2lpwr 6 r/w 0x00 enable low power mode for vgen2. refer to table 93 . unused 7 ? 0x00 unused table 96. register vgen3ctl - addr 0x6e name bit # r/w default description vgen3 3:0 r/w 0x80 sets vgen3 output voltage. see table 92 for all possible configurations. vgen3en 4 ? 0x00 enables or disables vgen3 output 0 = off 1 = on vgen3stby 5 r/w 0x00 set vgen3 output state when in standby. refer to table 93 . vgen3lpwr 6 r/w 0x00 enable low power mode for vgen3. refer to table 93 . unused 7 ? 0x00 unused
analog integrated circuit device data freescale semiconductor 87 pf0100 functional block requirements and behaviors power generation table 97. register vgen4ctl - addr 0x6f name bit # r/w default description vgen4 3:0 r/w 0x80 sets vgen4 output voltage. see table 92 for all possible configurations. vgen4en 4 ? 0x00 enables or disables vgen4 output 0 = off 1 = on vgen4stby 5 r/w 0x00 set vgen4 output state when in standby. refer to table 93 . vgen4lpwr 6 r/w 0x00 enable low power mode for vgen4. refer to table 93 . unused 7 ? 0x00 unused table 98. register vgen5ctl - addr 0x70 name bit # r/w default description vgen5 3:0 r/w 0x80 sets vgen5 output voltage. see table 92 for all possible configurations. vgen5en 4 ? 0x00 enables or disables vgen5 output 0 = off 1 = on vgen5stby 5 r/w 0x00 set vgen5 output state when in standby. refer to table 93 . vgen5lpwr 6 r/w 0x00 enable low power mode for vgen5. refer to table 93 . unused 7 ? 0x00 unused table 99. register vgen6ctl - addr 0x71 name bit # r/w default description vgen6 3:0 r/w 0x80 sets vgen6 output voltage. see table 92 for all possible configurations. vgen6en 4 ? 0x00 enables or disables vgen6 output 0 = off 1 = on vgen6stby 5 r/w 0x00 set vgen6 output state when in standby. refer to table 93 . vgen6lpwr 6 r/w 0x00 enable low power mode for vgen6. refer to table 93 . unused 7 ? 0x00 unused
analog integrated circuit device data 88 freescale semiconductor pf0100 functional block requi rements and behaviors power generation 7.4.6.4 external components table 100 lists the typical component values for the general purpose ldo regulators. 7.4.6.5 ldo specifications vgen1 table 100. ldo external components regulator output capacitor ( p f) (51) vgen1 2.2 vgen2 4.7 vgen3 2.2 vgen4 4.7 vgen5 2.2 vgen6 2.2 notes 51. use x5r/x7r ceramic capacitors. table 101. vgen1 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit vgen1 operating input voltage v in1 1.75?3.40v nominal output voltage vgen1 nom ? table 91 ?v operating load current i gen1 0.0 ? 100 ma vgen1 dc output voltage tolerance 1.75 v < v in1 < 3.4 v 0.0 ma < i gen1 < 100 ma vgen1[3:0] = 0000 to 1111 v gen1tol -3.0 ? 3.0 % load regulation (v gen1 at i gen1 = 100 ma) - (v gen1 at i gen1 = 0.0 ma) for any 1.75 v < v in1 < 3.4 v v gen1lor ?0.15? mv/ ma line regulation (v gen1 at v in1 = 3.4 v) - (v gen1 at v in1 = 1.75 v) for any 0.0 ma < i gen1 < 100 ma v gen1lir ?0.30? mv/ ma current limit i gen1 when vgen1 is forced to vgen1 nom /2 i gen1lim 133 167 200 ma over-current protection threshold i gen1 required to cause the scp function to disable ldo when regscpen = 1 i gen1ocp 120 ? 200 ma quiescent current no load, change in i vin and i vin1 when vgen1 enabled i gen1q ?14? p a
analog integrated circuit device data freescale semiconductor 89 pf0100 functional block requirements and behaviors power generation vgen1 ac and transient psrr (52) ?i gen1 = 75 ma, 20 hz to 20 khz vgen1[3:0] = 0000 - 1101 vgen1[3:0] = 1110, 1111 psrr vgen1 50 37 60 45 ? ? db output noise density v in1 = 1.75 v, i gen1 = 75 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz noise vgen1 ? ? ? -108 -118 -124 -100 -108 -112 dbv/ ? hz turn-on slew rate ? 10% to 90% of end value ?1.75 v d v in1 d 3.4 v, i gen1 = 0.0 ma vgen1[3:0] = 0000 to 0111 vgen1[3:0] = 1000 to 1111 slwr vgen1 ? ? ? ? 12.5 16.5 mv p s turn-on time enable to 90% of end value, v in1 = 1.75 v, 3.4 v i gen1 = 0.0 ma gen1 ton 60 ? 500 p s turn-off time disable to 10% of initial value, v in1 = 1.75 v i gen1 = 0.0 ma gen1 toff ??10ms start-up overshoot v in1 = 1.75 v, 3.4 v, i gen1 = 0.0 ma gen1 osht ?1.02.0% transient load response ?v in1 = 1.75 v, 3.4 v i gen1 = 10 to 100 ma in 1.0 p s. peak of overshoot or undershoot of vgen1 with respect to final value ? refer to figure 24 v gen1lotr ??3.0% transient line response ?i gen1 = 75 ma vin1 initial = 1.75 v to vin1 final = 2.25 v for vgen1[3:0] = 0000 to 1101 vin1 initial = v gen1 +0.3 v to vin1 final = v gen1 +0.8 v for vgen1[3:0] = 1110, 1111 ? refer to figure 24 v gen1litr ?5.08.0mv notes 52. the psrr of the regulators is measured with the perturbing signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken n ot to operate in the dropout region of the regulator under test. table 101. vgen1 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 90 freescale semiconductor pf0100 functional block requi rements and behaviors power generation vgen2 table 102. vgen2 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in1 = 3.0 v, v gen2 [3:0] = 1111, i gen2 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6v, v in1 = 3.0 v, vgen2[3:0] = 1111, i gen2 = 10ma and 25c, unless otherwise noted. parameter symbol min typ max unit vgen2 operating input voltage v in1 1.75?3.40v nominal output voltage vgen2 nom ? table 91 ?v operating load current i gen2 0.0 ? 250 ma vgen2 active mode - dc output voltagetolerance 1.75 v < v in1 < 3.4 v 0.0 ma < i gen2 < 250 ma vgen2[3:0] = 0000 to 1111 v gen2tol -3.0 ? 3.0 % load regulation (v gen2 at i gen2 = 250 ma) - (v gen2 at i gen2 = 0.0 ma) for any 1.75 v < v in1 < 3.4 v v gen2lor ?0.05? mv/ ma line regulation (v gen2 at v in1 = 3.4 v) - (v gen2 at v in1 = 1.75 v) for any 0.0 ma < i gen2 < 250 ma v gen2lir ?0.50? mv/ ma current limit i gen2 when vgen2 is forced to vgen2 nom /2 i gen2lim 333 417 500 ma over-current protection threshold i gen2 required to cause the scp function to disable ldo when regscpen = 1 i gen2ocp 300 ? 500 ma quiescent current no load, change in i vin and i vin1 when vgen2 enabled i gen2q ?16? p a vgen2 ac and transient psrr (53) ?i gen2 = 187.5 ma, 20 hz to 20 khz vgen2[3:0] = 0000 - 1101 vgen2[3:0] = 1110, 1111 psrr vgen2 50 37 60 45 ? ? db output noise density ?v in1 = 1.75 v, i gen2 = 187.5 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz noise vgen2 ? ? ? -108 -118 -124 -100 -108 -112 dbv/ ? hz turn-on slew rate ? 10% to 90% of end value ?1.75 v d v in1 d 3.4 v , i gen2 = 0.0 ma vgen2[3:0] = 0000 to 0111 vgen2[3:0] = 1000 to 1111 slwr vgen2 ? ? ? ? 12.5 16.5 mv p s turn-on time enable to 90% of end value, v in1 = 1.75 v, 3.4 v i gen2 = 0.0 ma gen2 ton 60 ? 500 p s
analog integrated circuit device data freescale semiconductor 91 pf0100 functional block requirements and behaviors power generation vgen2 ac and transient (continued) turn-off time disable to 10% of initial value, v in1 = 1.75 v i gen2 = 0.0 ma gen2 toff ??10ms start-up overshoot v in1 = 1.75 v, 3.4 v, i gen2 = 0.0 ma gen2 osht ?1.02.0% transient load response v in1 = 1.75 v, 3.4 v i gen2 = 25 to 250 ma in 1.0 p s peak of overshoot or undershoot of vgen2 with respect to final value refer to figure 24 v gen2lotr ??3.0% transient line response i gen2 = 187.5 ma vin1 initial = 1.75 v to vin1 final = 2.25 v for vgen2[3:0] = 0000 to 1101 vin1 initial = v gen2 +0.3 v to vin1 final = v gen2 +0.8 v for vgen2[3:0] = 1110, 1111 refer to figure 24 v gen2litr ?5.08.0mv notes 53. the psrr of the regulators is measured with the perturbing signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken n ot to operate in the dropout region of the regulator under test. table 102. vgen2 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in1 = 3.0 v, v gen2 [3:0] = 1111, i gen2 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6v, v in1 = 3.0 v, vgen2[3:0] = 1111, i gen2 = 10ma and 25c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 92 freescale semiconductor pf0100 functional block requi rements and behaviors power generation vgen3 table 103. vgen3 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit vgen3 operating input voltage 1.8 v d vgen3 nom d 2.5 v 2.6 v d vgen3 nom d 3.3 v (54) v in2 2.8 vgen3 nom + 0.250 ? ? 3.6 3.6 v nominal output voltage vgen3 nom ? table 92 ?v operating load current i gen3 0.0 ? 100 ma vgen3 dc output voltage tolerance vin2 min < v in2 < 3.6 v 0.0 ma < i gen3 < 100 ma vgen3[3:0] = 0000 to 1111 v gen3tol -3.0 ? 3.0 % load regulation (v gen3 at i gen3 = 100 ma) - (v gen3 at i gen3 = 0.0 ma) for any vin2 min < v in2 < 3.6 v v gen3lor ?0.07? mv/ ma line regulation (v gen3 at v in2 = 3.6 v) - (v gen3 at vin2 min ) for any 0.0 ma < i gen3 < 100 ma v gen3lir ?0.8? mv/ ma current limit i gen3 when vgen3 is forced to vgen3 nom /2 i gen3lim 133 167 200 ma over-current protection threshold i gen3 required to cause the scp function to disable ldo when regscpen = 1 i gen3ocp 120 ? 200 ma quiescent current no load, change in i vin and i vin2 when vgen3 enabled i gen3q ?13? p a vgen3 ac and transient psrr (55) ?i gen3 = 75 ma, 20 hz to 20 khz vgen3[3:0] = 0000 - 1110, v in2 = vin2 min + 100 mv vgen3[3:0] = 0000 - 1000, v in2 = vgen3 nom + 1.0 v psrr vgen3 35 55 40 60 ? ? db output noise density ?v in2 = vin2 min , i gen3 = 75 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz noise vgen3 ? ? ? -114 -129 -135 -102 -123 -130 dbv/ ? hz turn-on slew rate ? 10% to 90% of end value ?vin2 min d v in2 d 3.6 v , i gen3 = 0.0 ma vgen3[3:0] = 0000 to 0011 vgen3[3:0] = 0100 to 0111 vgen3[3:0] = 1000 to 1011 vgen3[3:0] = 1100 to 1111 slwr vgen3 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv p s
analog integrated circuit device data freescale semiconductor 93 pf0100 functional block requirements and behaviors power generation vgen3 ac and transient (continued) turn-on time enable to 90% of end value, v in2 = vin2 min , 3.6 v i gen3 = 0.0 ma gen3 ton 60 ? 500 p s turn-off time disable to 10% of initial value, v in2 = vin2 min i gen3 = 0.0 ma gen3 toff ??10ms start-up overshoot v in2 = vin2 min , 3.6 v, i gen3 = 0.0 ma gen3 osht ?1.02.0% transient load response v in2 = vin2 min , 3.6 v i gen3 = 10 to 100 ma in 1.0 p s peak of overshoot or undershoot of vgen3 with respect to final value. refer to figure 24 v gen3lotr ??3.0% transient line response i gen3 = 75 ma vin2 initial = 2.8 v to vin2 final = 3.3 v for gen3[3:0] = 0000 to 0111 vin2 initial = v gen3 +0.3 v to vin2 final = v gen3 +0.8 v for vgen3[3:0] = 1000 to 1010 vin2 initial = v gen3 +0.25 v to vin2 final = 3.6 v for vgen3[3:0] = 1011 to 1111 refer to figure 24 v gen3litr ?5.08.0mv notes 54. when the ldo output voltage is set above 2.6 v, the minimum al lowed input voltage needs to be at least the output voltage pl us 0.25 v, for proper regulation due to the dropout voltage generated through the internal ldo transistor. 55. the psrr of the regulators is measured with the perturbing signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken n ot to operate in the dropout region of the regulator under test. vin2 min refers to the minimum allowed input voltage for a particular output voltage. table 103. vgen3 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 94 freescale semiconductor pf0100 functional block requi rements and behaviors power generation vgen4 table 104. vgen4 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit vgen4 operating input voltage 1.8 v d vgen4 nom d 2.5 v 2.6 v d vgen4 nom d 3.3 v (56) v in2 2.8 vgen4 nom + 0.250 ? ? 3.6 3.6 v nominal output voltage vgen4 nom ? table 92 ?v operating load current i gen4 0.0 ? 350 ma vgen4 dc output voltage tolerance vin2 min < v in2 < 3.6 v 0.0 ma < i gen4 < 350 ma vgen4[3:0] = 0000 to 1111 v gen4tol -3.0 ? 3.0 % load regulation (v gen4 at i gen4 = 350 ma) - (v gen4 at i gen4 = 0.0 ma ) for any vin2 min < v in2 < 3.6 v v gen4lor ?0.07? mv/ ma line regulation (v gen4 at 3.6 v) - (v gen4 at vin2 min ) for any 0.0 ma < i gen4 < 350 ma v gen4lir ?0.80? mv/ ma current limit i gen4 when vgen4 is forced to vgen4 nom /2 i gen4lim 465.5 584.5 700 ma over-current protection threshold i gen4 required to cause the scp function to disable ldo when regscpen = 1 i gen4ocp 420 ? 700 ma quiescent current no load, change in i vin and i vin2 when vgen4 enabled i gen4q ?13? p a vgen4 ac and transient psrr (57) ?i gen4 = 262.5 ma, 20 hz to 20 khz vgen4[3:0] = 0000 - 1110, v in2 = vin2 min + 100 mv vgen4[3:0] = 0000 - 1000, v in2 = vgen4 nom + 1.0 v psrr vgen4 35 55 40 60 ? ? db output noise density ?v in2 = vin2 min , i gen4 = 262.5 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz noise vgen4 ? ? ? -114 -129 -135 -102 -123 -130 dbv/ ? hz turn-on slew rate ? 10% to 90% of end value ?vin2 min d v in2 d 3.6 v , i gen4 = 0.0 ma vgen4[3:0] = 0000 to 0011 vgen4[3:0] = 0100 to 0111 vgen4[3:0] = 1000 to 1011 vgen4[3:0] = 1100 to 1111 slwr vgen4 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv p s
analog integrated circuit device data freescale semiconductor 95 pf0100 functional block requirements and behaviors power generation vgen4 ac and transient (continued) turn-on time enable to 90% of end value, v in2 = vin2 min , 3.6 v i gen4 = 0.0 ma gen4 ton 60 ? 500 p s turn-off time disable to 10% of initial value, v in2 = vin2 min i gen4 = 0.0 ma gen4 toff ??10ms start-up overshoot v in2 = vin2 min , 3.6 v, i gen4 = 0.0 ma gen4 osht ?1.02.0% transient load response v in2 = vin2 min , 3.6 v i gen4 = 35 to 350 ma in 1.0 p s peak of overshoot or undershoot of vgen4 with respect to final value. refer to figure 24 v gen4lotr ??3.0% transient line response i gen4 = 262.5 ma vin2 initial = 2.8 v to vin2 final = 3.3 v for vgen4[3:0] = 0000 to 0111 vin2 initial = v gen4 +0.3 v to vin2 final = v gen4 +0.8 v for vgen4[3:0] = 1000 to 1010 vin2 initial = v gen4 +0.25 v to vin2 final = 3.6 v for vgen4[3:0] = 1011 to 1111 refer to figure 24 v gen4litr ?5.08.0mv notes 56. when the ldo output voltage is set above 2.6 v the minimum allowed input voltage need to be at least the output voltage plus 0.25 v for proper regulation due to the dropout voltage generated through the internal ldo transistor. 57. the psrr of the regulators is measured with the perturbing signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken n ot to operate in the dropout region of the regulator under test. vin2 min refers to the minimum allowed input voltage for a particular output voltage. table 104. vgen4 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 96 freescale semiconductor pf0100 functional block requi rements and behaviors power generation vgen5 table 105. vgen5 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, vin3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit vgen5 operating input voltage 1.8 v d vgen5 nom d 2.5 v 2.6 v d vgen5 nom d 3.3 v (58) v in3 2.8 vgen5 nom + 0.250 ? ? 4.5 4.5 v nominal output voltage vgen5 nom ? table 92 ?v operating load current i gen5 0.0 ? 100 ma vgen5 active mode ? dc output voltage tolerance vin3 min < v in3 < 4.5 v 0.0 ma < i gen5 < 100 ma vgen5[3:0] = 0000 to 1111 v gen5tol -3.0 ? 3.0 % load regulation (v gen5 at i gen5 = 100 ma) - (v gen5 at i gen5 = 0.0 ma) for any vin3 min < v in3 < 4.5 mv v gen5lor ?0.10? mv/ ma line regulation (v gen5 at v in3 = 4.5 v) - (v gen5 at vin3 min ) for any 0.0 ma < i gen5 < 100 ma v gen5lir ?0.50? mv/ ma current limit i gen5 when vgen5 is forced to vgen5 nom /2 i gen5lim 133 167 200 ma over-current protection threshold i gen5 required to cause the scp function to disable ldo when regscpen = 1 i gen5ocp 120 ? 200 ma quiescent current no load, change in i vin and i vin3 when vgen5 enabled i gen5q ?13? p a vgen5 ac and transient psrr (59) ?i gen5 = 75 ma, 20 hz to 20 khz vgen5[3:0] = 0000 - 1111, v in3 = vin3 min + 100 mv vgen5[3:0] = 0000 - 1111, v in3 = vgen5 nom + 1.0 v psrr vgen5 35 52 40 60 ? ? db output noise density ?v in3 = vin3 min , i gen5 = 75 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz noise vgen5 ? ? ? -114 -129 -135 -102 -123 -130 dbv/ ? hz turn-on slew rate ? 10% to 90% of end value ?vin3 min d v in3 d 4.5 mv , i gen5 = 0.0 ma vgen5[3:0] = 0000 to 0011 vgen5[3:0] = 0100 to 0111 vgen5[3:0] = 1000 to 1011 vgen5[3:0] = 1100 to 1111 slwr vgen5 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv p s
analog integrated circuit device data freescale semiconductor 97 pf0100 functional block requirements and behaviors power generation vgen5 active mode ? dc (continued) turn-on time enable to 90% of end value, v in3 = vin3 min , 4.5 v i gen5 = 0.0 ma gen5 ton 60 ? 500 p s turn-off time disable to 10% of initial value, v in3 = vin3 min i gen5 = 0.0 ma gen5 toff ??10ms start-up overshoot v in3 = vin3 min , 4.5 v, i gen5 = 0.0 ma gen5 osht ?1.02.0% transient load response v in3 = vin3 min , 4.5 v i gen5 = 10 to 100 ma in 1.0 p s peak of overshoot or undershoot of vgen5 with respect to final value. refer to figure 24 v gen5lotr ??3.0% transient line response i gen5 = 75 ma vin3 initial = 2.8 v to vin3 final = 3.3 v for vgen5[3:0] = 0000 to 0111 vin3 initial = v gen5 +0.3 v to vin3 final = v gen5 +0.8 v for vgen5[3:0] = 1000 to 1111 refer to figure 24 v gen5litr -5.08.0mv notes 58. when the ldo output voltage is set above 2.6 v the minimum allowed input voltage need to be at least the output voltage plus 0.25 v for proper regulation due to the dropout voltage generated through the internal ldo transistor. 59. the psrr of the regulators is measured with the perturbing signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken n ot to operate in the dropout region of the regulator under test. vin3 min refers to the minimum allowed input voltage for a particular output voltage. table 105. vgen5 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, vin3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data 98 freescale semiconductor pf0100 functional block requi rements and behaviors power generation vgen6 table 106. vgen6 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit vgen6 operating input voltage 1.8 v d vgen6 nom d 2.5 v 2.6 v d vgen6 nom d 3.3 v (60) v in3 2.8 vgen6 nom + 0.250 ? ? 4.5 4.5 v nominal output voltage vgen6 nom ? table 92 ?v operating load current i gen6 0.0 ? 200 ma vgen6 dc output voltage tolerance vin3 min < v in3 < 4.5 v 0.0 ma < i gen6 < 200 ma vgen6[3:0] = 0000 to 1111 v gen6tol -3.0 ? 3.0 % load regulation (v gen6 at i gen6 = 200 ma) - (v gen6 at i gen6 = 0.0 ma) for any vin3 min < v in3 < 4.5 v v gen6lor ?0.10? mv/ ma line regulation (v gen6 at v in3 = 4.5 v) - (v gen6 at vin3 min ) for any 0.0 ma < i gen6 < 200 ma v gen6lir ?0.50? mv/ ma current limit i gen6 when vgen6 is forced to vgen6 nom /2 i gen6lim 240 333 400 ma over current protection threshold i gen6 required to cause the scp function to disable ldo when regscpen = 1 i gen6ocp 240 ? 400 ma quiescent current no load, change in i vin and i vin3 when vgen6 enabled i gen6q ?13? p a vgen6 ac and transient psrr (61) ?i gen6 = 150 ma, 20 hz to 20 khz vgen6[3:0] = 0000 - 1111, v in3 = vin3 min + 100 mv vgen6[3:0] = 0000 - 1111, v in3 = vgen6 nom + 1.0 v psrr vgen6 35 52 40 60 ? ? db output noise density ?v in3 = vin3 min , i gen6 = 150 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz noise vgen6 ? ? ? -114 -129 -135 -102 -123 -130 dbv/ ? hz turn-on slew rate ? 10% to 90% of end value ?vin3 min d v in3 d 4.5 v . i gen6 = 0.0 ma vgen6[3:0] = 0000 to 0011 vgen6[3:0] = 0100 to 0111 vgen6[3:0] = 1000 to 1011 vgen6[3:0] = 1100 to 1111 slwr vgen6 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv p s turn-on time enable to 90% of end value, v in3 = vin3 min , 4.5 v i gen6 = 0.0 ma gen6 ton 60 ? 500 p s
analog integrated circuit device data freescale semiconductor 99 pf0100 functional block requirements and behaviors power generation 7.4.7 vsnvs ldo/switch vsnvs powers the low power, snvs/rtc domain on the processor. it derives its power from either vin, or co in cell, and cannot be disabled. when powered by both, vin takes precedence when above the appropriate comparat or threshold. when powered by vin, vsnvs is an ldo capable of supplying seven vo ltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 v. the bits vsnvsvolt[2:0] in register vsnvs_control determine the output voltage. when powered by coin cell , vsnvs is an ldo capable of supplying 1.8, 1.5, 1.3, 1. 2, 1.1, or 1.0 v as shown in table 107 . if the 3.0 v option is chosen with the coin cell, vsnvs tracks the coin cell voltage by means of a switch, whose maximum resistance is 100 : . in this case, the vsnvs volt age is simply the coin cell voltage minus the voltage drop across the switch, which is 40 mv at a rated maximum load current of 400 p a. the default setting of the vsnvsvo lt[2:0] is 110, or 3.0 v, unless programmed otherwise in otp. however, when the coin cell is applied for the very first time, vsnvs will output 1.0 v. only when vin is applied thereafter will vsnvs transition to its default, or programmed value if different. upon subsequent removal of vin, with the coin cell attached, vsnvs will change configuration from an ldo to a switch for the ?110? setting, and will remain as an ldo for the other settings, continuing to output the same voltages as when vin is applied, providing certain conditions are met as described in table 107 . vgen6 ac and transient (continued) turn-off time disable to 10% of initial value, v in3 = vin3 min i gen6 = 0.0 ma gen6 toff ??10ms start-up overshoot v in3 = vin3 min , 4.5 v, i gen6 = 0 ma gen6 osht ?1.02.0% transient load response v in3 = vin3 min , 4.5 v i gen6 = 20 to 200 ma in 1.0 p s peak of overshoot or undershoot of vgen6 with respect to final value. refer to figure 24 v gen6lotr ??3.0% transient line response i gen6 = 150 ma vin3 initial = 2.8 v to vin3 final = 3.3 v for vgen6[3:0] = 0000 to 0111 vin3 initial = v gen6 +0.3 v to vin3 final = v gen6 +0.8 v for vgen6[3:0] = 1000 to 1111 refer to figure 24 v gen6litr ?5.08.0mv notes 60. when the ldo output voltage is set above 2.6 v the minimum allowed input voltage need to be at least the output voltage plus 0.25 v for proper regulation due to the dropout voltage generated through the internal ldo transistor. 61. the psrr of the regulators is measured with the perturbing signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken n ot to operate in the dropout region of the regulator under test. vin3 min refers to the minimum allowed input voltage for a particular output voltage. table 106. vgen6 elect rical characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, and 25 c, unless otherwise noted. parameter symbol min typ max unit
ldo\ pf0100 vsnvs coin cell 1.8 - 3.3 v v in 2.25 v (vtl0) - 4.5 v licell charger ldo/switch v ref + _ z input sense/ selector i 2 c interface analog integrated circuit device data 100 freescale semiconductor pf0100 functional block requi rements and behaviors power generation figure 25. vsnvs supply switch architecture table 107 provides a summary of the vsnvs operation at different input voltage vin and with or without coin cell connected to the system. vsnvs control the vsnvs output level is configured through the vsnvsvolt [2:0]bits on vsnvsctl register as shown in table table 108 . vsnvs external components table 107. vsnvs modes of operation vsnvsvolt[2:0] vin mode 110 > vth1 vin ldo 3.0 v 110 < vtl1 coin cell switch 000 ? 101 > vth0 vin ldo 000 ? 101 < vtl0 coin cell ldo table 108. register vsnvsctl - addr 0x6b name bit # r/w default description vsnvsvolt 2:0 r/w 0x80 configures vsnvs output voltage. (62) 000 = 1.0 v 001 = 1.1 v 010 = 1.2 v 011 = 1.3 v 100 = 1.5 v 101 = 1.8 v 110 = 3.0 v 111 = rsvd unused 7:3 ? 0x00 unused notes 62. only valid when a valid input voltage is present. table 109. vsnvs external components capacitor value ( f) vsnvs 0.47
analog integrated circuit device data freescale semiconductor 101 pf0100 functional block requirements and behaviors power generation vsnvs specifications table 110. vsnvs electri cal characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 p a, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 p a, and 25 c, unless otherwise noted. parameter symbol min typ max unit vsnvs operating input voltage valid coin cell range valid v in vin snvs 1.8 2.25 ? ? 3.3 4.5 v operating load current v inmin < v in < v inmax i snvs 5.0 ? 400 (63) p a vsnvs dc, ldo output voltage ?5.0 p a < i snvs < 400 p a (off) 3.20 v < v in < 4.5 v, vsnvsvolt[2:0] = 110 vtl0/vth < v in < 4.5 v, vsnvsvolt[2:0] = [000] - [101] ?5.0 p a < i snvs < 400 p a (on) 3.20 v < v in < 4.5 v, vsnvsvolt[2:0] = 110 uvdet < v in < 4.5 v, vsnvsvolt[2:0] = [000] - [101] ?5 0 p a < i snvs < 400 p a (coin cell mode) 2.84 v < v coin < 3.3 v, vsnvsvolt[2:0] = 110 1.8 v < v coin < 3.3 v, vsnvsvolt[2:0] = [000] - [101] (65) v snvs -5.0% -8.0% -5.0% -4.0% v coin -0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 ? 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% v coin 7.0% v dropout voltage 2.85 v < v in < 2.9 v, vsnvsvolt[2:0] = 110 5.0 p a < i snvs < 400 p a vsnvs drop ??50mv current limit v in > v th1 , vsnvsvolt[2:0] = 110 v in > v tl0 , vsnvsvolt[2:0] = 000 to 101 v in < v tl0 , vsnvsvolt[2:0] = 000 to 101 isnvs lim 750 500 480 ? ? ? 5900 5900 3600 p a v in threshold (coin cell powered to v in powered) v in going high with valid coin cell vsnvsvolt[2:0] = 000, 001, 010, 011, 100, 101 v th0 2.25 2.40 2.50 v v in threshold (v in powered to coin cell powered) v in going low with valid coin cell vsnvsvolt[2:0] = 000, 001, 010, 011, 100, 101 v tl0 2.20 2.35 2.45 v v in threshold hysteresis for v th1 -v tl1 v hyst1 5.0 ? ? mv v in threshold hysteresis for v th0 -v tl0 v hyst0 5.0 ? ? mv output voltage during crossover vsnvsvolt[2:0] = 110 v coin > 2.9 v switch to ldo: v in > 2.825 v, i snvs = 100 p a ldo to switch: v in < 3.05 v, i snvs = 100 p a vsnvs cross 2.80 ? ? v
analog integrated circuit device data 102 freescale semiconductor pf0100 functional block requi rements and behaviors power generation vsnvs ac and transient turn-on time (64) (load capacitor, 0.47 p f) v coin = 3.0 v to 90% of v snvs v in = 0.0 v, i snvs = 5.0 p a vsnvsvolt[2:0] = 000 to 110 v in = vth0 to 90% of v snvs v coin = 0.0 v, i snvs = 5.0 p a vsnvsvolt[2:0] = 000 to 110 ton snvs ??24ms start-up overshoot vsnvsvolt[2:0] = 000 to 110 i snvs = 5.0 p a dv in /dt = 50 mv/ p s v snvsosh ?4070mv transient line response i snvs = 75% of isnvs max 3.2 v < v in < 4.5 v, vsnvsvolt[2:0] = 110 2.45 v < v in < 4.5 v, vsnvsvolt[2:0] = [000] - [101] v snvslitr ? ? 32 22 ? ? mv transient load response vsnvsvolt[2:0] = 110 3.1 v (uvdetl)< v in d 4.5 v i snvs = 75 to 750 p a vsnvsvolt[2:0] = 000 to 101 2.45 v < v in d 4.5 v vtl0 > vin, 1.8 v d v coin d 3.3 v i snvs = 40 to 400 p a refer to figure 24 v snvslotr 2.8 ? ? 1.0 ? 2.0 v % vsnvs dc, switch operating input voltage valid coin cell range v insnvs 1.8 ? 3.3 v operating load current i snvs 5.0 ? 400 p a internal switch rdson v coin = 2.6 v r dsonsnvs ? ? 100 : v in threshold (v in powered to coin cell powered) vsnvsvolt[2:0] = 110 vtl1 2.825 2.90 3.00 v v in threshold (coin cell powered to v in powered) vsnvsvolt[2:0] = 110 vth1 2.85 2.95 3.05 v notes 63. current required by i.mx6x snvs domain may change. 64. the start-up of vsnvs is not monotonic. it first rises to 1. 0 v and then settles to its programmed value within the specifie d tr 1 time. 65. for 1.8 v i snvs limited to 100 p a for v coin < 2.1 v table 110. vsnvs electri cal characteristics all parameters are specified at t a = -40 to 85 c, v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 p a, typical external component values, unless otherwise noted. typical values are characterized at v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 p a, and 25 c, unless otherwise noted. parameter symbol min typ max unit
analog integrated circuit device data freescale semiconductor 103 pf0100 functional block requirements and behaviors power generation 7.4.7.1 coin cell battery backup the licell pin provides for a connection of a coin cell backup ba ttery or a ?super? capacitor. if the voltage at vin goes below the v in threshold (v tl1 and v tl0 ), contact-bounced, or removed, the coin cell maintained logic will be powered by the voltage applied to licell. a small capacitor should be plac ed from licell to ground under all circumstances. coin cell charger control the coin cell charger circuit will function as a current-limited voltage source, result ing in the cc/cv taper characteristic ty pically used for rechargeable lithium-ion batteries. the coin cell char ger is enabled via the coinchen bit while the coin cell voltage is programmable through the vcoin[2: 0] bits on register coinctl on table 112 . the coin cell charger voltage is programmable. in the on state, the charger current is fixed at icoinhi. in sleep and st andby modes, the charger current is fixed at icoinlo as indicated in table 114 .in the off state, coin cell c harging is not available as the main battery could be depleted unnecessarily. the coin cell charging will be stopped when v in is below uvdet. external components table 111. coin cell charger voltage vcoin[2:0] v coin (v) (66) 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 notes 66. coin cell voltages selected based on the type of licell used on the system. table 112. register coinctl - addr 0x1a name bit # r/w default description vcoin 2:0 r/w 0x00 coin cell charger output voltage selection. see table 111 for all options selectable through these bits. coinchen 3 r/w 0x00 enable or di sable the coin cell charger unused 7:4 ? 0x00 unused table 113. coin cell charger external components component value units licell bypass capacitor 100 nf licell bypass capacitor as coin cell replacement 4.7 p f
analog integrated circuit device data 104 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description coin cell specifications 7.5 control interface i 2 c block description the pf0100 contains an i 2 c interface port which allows access by a processor, or any i 2 c master, to the register set. via these registers the resources of the ic can be controlled. the registers also provide stat us information about how the ic is operatin g. 7.5.1 i 2 c device id i 2 c interface protocol requires a device id for addressing the targ et ic on a multi-device bus. to allow flexibility in addressin g for bus conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address lsb(s). refer to one time programmability (otp) for more details. this product supports 7-bit addressing o nly; support is not provided for 10-bit or general call addressing. note, when the tbb bits for the i 2 c slave address are written, the next ac cess to the chip, must then use the new slave address; these bits take affect right away. 7.5.2 i 2 c operation the i 2 c mode of the interface is implemented generally follo wing the fast mode definition which supports up to 400 kbits/s ope ration (exceptions to the standard are noted to be 7-bit on ly addressing and no support for general call addressing.) timing diagrams, electrical specifications, an d further details can be found in the i 2 c specification, which is available for download at: http://www.nxp.com/ac ro bat_download/literature/9398/39340011.pdf i 2 c read operations are also performed in byte increments sepa rated by an ack. read operations also begin with the msb and each byte will be sent out unless a stop command or nack is received prior to completion. the following examples show how to write and read data to and fr om the ic. the host initiates and terminates all communication. the host sends a master command packet after driving the start co ndition. the device will respond to the host if the master command packet contains the corresponding sl ave address. in the following examples , the device is shown always responding with an ack to transmissions from the host. if at any time a nack is received, the host should terminate the current transactio n and retry the transaction. device a dd ress reg ister addre ss packe t t y pe start r / w host sd a a c k slave sd a a c k m aster driven data ( byte 0) 0 7 stop host can also drive anothe r start instead of stop a c k 0 0 7 0 7 figure 26. i 2 c write example table 114. coin cell charger specifications parameter typ unit voltage accuracy 100 mv coin cell charge current in on mode icoinhi 60 a current accuracy 30 %
device address register address device address packet type start 0 r/w 16 23 8 15 0 7 a c k stop a c k a c k start 0 7 r/w na ck pmic driven data host can also drive another start instead of stop 1 host sda slave sda analog integrated circuit device data freescale semiconductor 105 pf0100 functional block requirements and behaviors control interface i2c block description figure 27. i 2 c read example 7.5.3 interrupt handling the system is informed about important events based on interrupts. unmaske d interrupt events are signaled to the processor by driving the intb pin low. each interrupt is latched so that even if the interrupt source become s inactive, the interrupt will remain set until cleared. e ach interrupt can be cleared by writing a ?1? to the appropriate bi t in the interrupt status register; this will also cause the int b pin to go high. if there are multiple in terrupt bits set the intb pin will remain low until all are either masked or cleared. if a new interrupt occurs while the processor clears an existing interrupt bit, the intb pin will remain low. each interrupt can be masked by setting the corresponding mask bit to a 1. as a resul t, when a masked interrupt bit goes high, the intb pin will not go low. a masked interrupt can still be read from the interrupt status register. this gives the processor the option of polling for status from the ic. the ic powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active . alternatively, the processor can unmask th e interrupt bits of interest. if a masked interrupt bit was already high, the intb pin will go low after unmasking. the sense registers contain status and input sense bits so the sy stem p rocessor can poll the curr ent state of interrupt sources . they are read only, and not latched or clearable. interrupts generated by external events ar e deb ounced; therefore, the event needs to be stable throughout the debounce period before an interrupt is gener ated. nominal debounce periods for each ev ent are documented in the int summary table 115 . due to the asynchronous nature of the debounce timer, th e effective debounce ti me can vary slightly. 7.5.4 interrupt bit summary table 115 summarizes all interrupt, mask, and sense bits asso ciated with intb control. fo r more detailed behavioral descriptions, refer to the related chapters. table 115. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time (ms) lowvini lowvinm lowvins low input voltage detect sense is 1 if below 2.80 v threshold h to l 3.9 (67) pwroni pwronm pwrons power on button event h to l 31.25 (67) sense is 1 if pwron is high. l to h 31.25 therm110 therm110m therm110s thermal 110 c threshold sense is 1 if above threshold dual 3.9 therm120 therm120m therm120s thermal 120 c threshold sense is 1 if above threshold dual 3.9 therm125 therm125m therm125s thermal 125 c threshold sense is 1 if above threshold dual 3.9 therm130 therm130m therm130s thermal 130 c threshold sense is 1 if above threshold dual 3.9 sw1afaulti sw1afaultm sw1afaults regulator 1a over-current limit sense is 1 if above current limit l to h 8.0 sw1bfaulti sw1bfaultm sw1bfaults regulator 1b over-current limit sense is 1 if above current limit l to h 8.0
analog integrated circuit device data 106 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description a full description of all interrupt, mask, and sense registers is provided in tables 116 to 127 . sw1cfaulti sw1cfaultm sw1cfaults regulator 1c over-current limit sense is 1 if above current limit l to h 8.0 sw2faulti sw2faultm sw2faults regulator 2 over-current limit sense is 1 if above current limit l to h 8.0 sw3afaulti sw3afaultm sw3afaults regulator 3a over-current limit sense is 1 if above current limit l to h 8.0 sw3bfaulti sw3bfaultm sw3bfaults regulator 3b over-current limit sense is 1 if above current limit l to h 8.0 sw4faulti sw4faultm sw4faults regulator 4 over-current limit sense is 1 if above current limit l to h 8.0 swbstfaulti swbstfaultm swbstfaults swbst over-current limit sense is 1 if above current limit l to h 8.0 vgen1faulti vgen1faultm vgen1faults vgen1 over-current limit sense is 1 if above current limit l to h 8.0 vgen2faulti vgen2faultm vgen2faults vgen2 over-current limit sense is 1 if above current limit l to h 8.0 vgen3faulti vgen3faultm vgen3faults vgen3 over-current limit sense is 1 if above current limit l to h 8.0 vgen4faulti vgen4faultm vgen4faults vgen4 over-current limit sense is 1 if above current limit l to h 8.0 vgen5faulti vgen5faultm vgen1faults vgen5 over-current limit sense is 1 if above current limit l to h 8.0 vgen6faulti vgen6faultm vgen6faults vgen6 over-current limit sense is 1 if above current limit l to h 8.0 otp_ecci otp_eccm otp_eccs 1 or 2 bit error detected in otp registers sense is 1 if error detected l to h 8.0 notes 67. debounce timing for the falling edge c an be extended with pwrondbnc[1:0]. table 116. register intstat0 - addr 0x05 name bit # r/w default description pwroni 0 r/w1c 0 power on interrupt bit lowvini 1 r/w1c 0 low-voltage interrupt bit therm110i 2 r/w1c 0 110 c thermal interrupt bit therm120i 3 r/w1c 0 120 c thermal interrupt bit therm125i 4 r/w1c 0 125 c thermal interrupt bit therm130i 5 r/w1c 0 130 c thermal interrupt bit unused 7:6 ? 00 unused table 115. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time (ms)
analog integrated circuit device data freescale semiconductor 107 pf0100 functional block requirements and behaviors control interface i2c block description table 117. register intmask0 - addr 0x06 name bit # r/w default description pwronm 0 r/w1c 0 power on interrupt mask bit lowvinm 1 r/w1c 0 low-voltage interrupt mask bit therm110m 2 r/w1c 0 110 c thermal interrupt mask bit therm120m 3 r/w1c 0 120 c thermal interrupt mask bit therm125m 4 r/w1c 0 125 c thermal interrupt mask bit therm130m 5 r/w1c 0 130 c thermal interrupt mask bit unused 7:6 ? 00 unused table 118. register intsense0 - addr 0x07 name bit # r/w default description pwrons 0 r 0 power on sense bit 0 = pwron low 1 = pwron high lowvins 1 r 0 low voltage sense bit 0 = vin > 2.8 v 1 = vin d 2.8 v therm110s 2 r 0 110 c thermal sense bit 0 = below threshold 1 = above threshold therm120s 3 r 0 120 c thermal sense bit 0 = below threshold 1 = above threshold therm125s 4 r 0 125 c thermal sense bit 0 = below threshold 1 = above threshold therm130s 5 r 0 130 c thermal sense bit 0 = below threshold 1 = above threshold unused 6 ? 0 unused vddotps 7 r 00 additional vddotp voltage sense pin 0 = vddotp grounded 1 = vddotp to vcoredig or greater table 119. register intstat1 - addr 0x08 name bit # r/w default description sw1afaulti 0 r/w1c 0 sw1a over-current interrupt bit sw1bfaulti 1 r/w1c 0 sw1b over-current interrupt bit sw1cfaulti 2 r/w1c 0 sw1c over-current interrupt bit sw2faulti 3 r/w1c 0 sw2 over-current interrupt bit sw3afaulti 4 r/w1c 0 sw3a over-current interrupt bit sw3bfaulti 5 r/w1c 0 sw3b over-current interrupt bit sw4faulti 6 r/w1c 0 sw4 over-current interrupt bit unused 7 ? 0 unused
analog integrated circuit device data 108 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description table 120. register intmask1 - addr 0x09 name bit # r/w default description sw1afaultm 0 r/w 1 sw1a over-current interrupt mask bit sw1bfaultm 1 r/w 1 sw1b over-current interrupt mask bit sw1cfaultm 2 r/w 1 sw1c over-current interrupt mask bit sw2faultm 3 r/w 1 sw2 over-current interrupt mask bit sw3afaultm 4 r/w 1 sw3a over-current interrupt mask bit sw3bfaultm 5 r/w 1 sw3b over-current interrupt mask bit sw4faultm 6 r/w 1 sw4 over-current interrupt mask bit unused 7 ? 0 unused table 121. register intsense1 - addr 0x0a name bit # r/w default description sw1afaults 0 r 0 sw1a over-current sense bit 0 = normal operation 1 = above current limit sw1bfaults 1 r 0 sw1b over-current sense bit 0 = normal operation 1 = above current limit sw1cfaults 2 r 0 sw1c over-current sense bit 0 = normal operation 1 = above current limit sw2faults 3 r 0 sw2 over-current sense bit 0 = normal operation 1 = above current limit sw3afaults 4 r 0 sw3a over-current sense bit 0 = normal operation 1 = above current limit sw3bfaults 5 r 0 sw3b over-current sense bit 0 = normal operation 1 = above current limit sw4faults 6 r 0 sw4 over-current sense bit 0 = normal operation 1 = above current limit unused 7 ? 0 unused table 122. register intstat3 - addr 0x0e name bit # r/w default description swbstfaulti 0 r/w1c 0 swbst over-current limit interrupt bit unused 6:1 ? 0x00 unused otp_ecci 7 r/w1c 0 otp error interrupt bit
analog integrated circuit device data freescale semiconductor 109 pf0100 functional block requirements and behaviors control interface i2c block description table 123. register intmask3 - addr 0x0f name bit # r/w default description swbstfaultm 0 r/w 1 swbst over-current limit interrupt mask bit unused 6:1 ? 0x00 unused otp_eccm 7 r/w 1 otp erro r interrupt mask bit table 124. register intsense3 - addr 0x10 name bit # r/w default description swbstfaults 0 r 0 swbst over-current limit sense bit 0 = normal operation 1 = above current limit unused 6:1 ? 0x00 unused otp_eccs 7 r 0 otp error sense bit 0 = no error detected 1 = otp error detected table 125. register intstat4 - addr 0x11 name bit # r/w default description vgen1faulti 0 r/w1c 0 vgen1 over-current interrupt bit vgen2faulti 1 r/w1c 0 vgen2 over-current interrupt bit vgen3faulti 2 r/w1c 0 vgen3 over-current interrupt bit vgen4faulti 3 r/w1c 0 vgen4 over-current interrupt bit vgen5faulti 4 r/w1c 0 vgen5 over-current interrupt bit vgen6faulti 5 r/w1c 0 vgen6 over-current interrupt bit unused 7:6 ? 00 unused table 126. register intmask4 - addr 0x12 name bit # r/w default description vgen1faultm 0 r/w 1 vgen1 over-c urrent interrupt mask bit vgen2faultm 1 r/w 1 vgen2 over-c urrent interrupt mask bit vgen3faultm 2 r/w 1 vgen3 over-c urrent interrupt mask bit vgen4faultm 3 r/w 1 vgen4 over-c urrent interrupt mask bit vgen5faultm 4 r/w 1 vgen5 over-c urrent interrupt mask bit vgen6faultm 5 r/w 1 vgen6 over-c urrent interrupt mask bit unused 7:6 ? 00 unused
analog integrated circuit device data 110 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description 7.5.5 specific registers 7.5.5.1 ic and version identification the ic and other version details can be read via identifi cation bits. these are hard-wired on chip and described in tables 128 to 130 . table 127. register intsense4 - addr 0x13 name bit # r/w default description vgen1faults 0 r 0 vgen1 over-current sense bit 0 = normal operation 1 = above current limit vgen2faults 1 r 0 vgen2 over-current sense bit 0 = normal operation 1 = above current limit vgen3faults 2 r 0 vgen3 over-current sense bit 0 = normal operation 1 = above current limit vgen4faults 3 r 0 vgen4 over-current sense bit 0 = normal operation 1 = above current limit vgen5faults 4 r 0 vgen5 over-current sense bit 0 = normal operation 1 = above current limit vgen6faults 5 r 0 vgen6 over-current sense bit 0 = normal operation 1 = above current limit unused 7:6 ? 00 unused table 128. register deviceid - addr 0x00 name bit # r/w default description deviceid 3:0 r 0x00 die version. 0000 = pf0100 unused 7:4 ? 0 unused table 129. register silicon rev- addr 0x03 name bit # r/w default description metal_layer_rev 3:0 r 0x00 represents the metal mask revision pass 0.0 = 0000 . . pass 0.15 = 1111 full_layer_rev 7:4 r 0x01 represents the full mask revision pass 1.0 = 0001 . . pass 15.0 = 1111
analog integrated circuit device data freescale semiconductor 111 pf0100 functional block requirements and behaviors control interface i2c block description 7.5.5.2 embedded memory there are four register banks of general purpose embedded memory to store critical data. the data written to mema[7:0], memb[7:0], memc[7:0], and memd[7 :0] is maintained by the coin cell when the ma in battery is deeply discharged, removed, or contact-bounced. the contents of the em bedded memory are reset by coinporb. th e banks can be used for any system need for bit retention with coin cell backup. table 130. register fabid - addr 0x04 name bit # r/w default description fin 1:0 r 0x00 allows for characterizing different options within the same reticule pass 1.0 = 00 fab 3:2 r 0x00 represents the wafer manufacturing facility pass 1.0 = 00 unused 7:0 r 0x00 unused table 131. register mema addr 0x1c name bit # r/w default description mema 7:0 r/w 0 memory bank a table 132. register memb addr 0x1d name bit # r/w default description memb 7:0 r/w 0 memory bank b table 133. register memc addr 0x1e name bit # r/w default description memc 7:0 r/w 0 memory bank c table 134. register memd addr 0x1f name bit # r/w default description memd 7:0 r/w 0 memory bank d
analog integrated circuit device data 112 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description 7.5.6 register bitmap the register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. only the first two pages can be accessed. on each page, registers 0 to 0x7f are referred to as 'functional' , and registers 0x80 to 0xff as 'extended' . on each page, the functional registers are the same, but th e extended registers are differ ent. to access registers on extended page 1 , one must first write 0x01 to the page register at address 0x7f, and to access registers extended page 2 , one must first write 0x02 to the page regi ster at address 0x7f. to access the functional page from one of the extended pages, no write to the page regi ster is necessary. registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will h ave no effect. the contents of all registers are given in the tables defined in this chapter ; each table is structure as follows: name: name of the bit. bit #: the bit location in the register (7-0) r/w: read / write access and control ? r is read-only access ? r/w is read and write access ? rw1c is read and write access with write 1 to clear reset: reset signals are color coded based on the following legend. default: the value after reset, as noted in the default column of the memory map. ? fixed defaults are explicitly declared as 0 or 1. ? ?x? corresponds to read / write bits that are initialized at start-up, based on the otp fu se settings or default if vddotp = 1.5 v. bits are subsequently i 2 c modifiable, when their reset has been released. ?x? may also refer to bits that may have other dependencies. for example, some bits may dep end on the version of the ic, or a value from an analog block, for instance the sense bits for the interrupts. 7.5.6.1 register map bits reset by sc and vcoredig_porb bits reset by pwron or loaded default or otp configuration bits reset by digresetb bits reset by porb or resetbmcu bits reset by vcoredig_porb bits reset by por or offb table 135. functional page bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0 00 deviceid r 8'b0001_0000 ? ? ? ? device id [3:0] 00 0 1 0 0 0 0 03 siliconrevid r 8'b0001_0000 full_layer_rev[3:0] metal_layer_rev[3:0] 00 0 1 0 0 0 0 04 fabid r 8'b0000_0000 ? ? ? ? fab[1:0] fin[1:0] 00 0 0 0 0 0 0 05 intstat0 rw1c 8'b0000_0000 ?? therm130i therm125i therm120i therm110i lowvini pwroni 00 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 113 pf0100 functional block requirements and behaviors control interface i2c block description 06 intmask0 r/w 8'b0011_1111 ?? therm130m therm125m therm120m therm110m lowvinm pwronm 00 1 1 1 1 1 1 07 intsense0 r 8'b00xx_xxxx vddotps rsvd therm130s therm125s therm120s therm110s lowvins pwrons 00 x x x x x x 08 intstat1 rw1c 8'b0000_0000 ? sw4faulti sw3bfaulti sw3afaulti sw2faulti sw1cfaulti sw1bfaulti sw1afaulti 00 0 0 0 0 0 0 09 intmask1 r/w 8'b0111_1111 ? sw4faultm sw3bfaultm sw3afaultm sw2faultm sw1cfaultm sw1bfaultm sw1afaultm 01 1 1 1 1 1 1 0a intsense1 r 8'b0xxx_xxxx ? sw4faults sw3bfaults sw3afaults sw2fau lts sw1cfaults sw1bfaults sw1afaults 0x x x x x x x 0e intstat3 rw1c 8'b0000_0000 otp_ecci ? ? ? ? ? ? swbstfaulti 00 0 0 0 0 0 0 0f intmask3 r/w 8'b1000_0001 otp_eccm ? ? ? ? ? ? swbstfaultm 10 0 0 0 0 0 1 10 intsense3 r 8'b0000_000x otp_eccs ? ? ? ? ? ? swbstfaults 00 0 0 0 0 0 x 11 intstat4 rw1c 8'b0000_0000 ?? vgen6faulti vgen5faulti vgen4faulti vgen3faulti vgen2faulti vgen1faulti 00 0 0 0 0 0 0 12 intmask4 r/w 8'b0011_1111 ?? vgen6 faultm vgen5 faultm vgen4 faultm vgen3 faultm vgen2 faultm vgen1 faultm 00 1 1 1 1 1 1 13 intsense4 r 8'b00xx_xxxx ?? vgen6 faults vgen5 faults vgen4 faults vgen3 faults vgen2 faults vgen1 faults 00 x x x x x x 1a coinctl r/w 8'b0000_0000 ?? ? ? coinchen vcoin[2:0] 00 0 0 0 0 0 0 1b pwrctl r/w 8'b0001_0000 regscpen standbyinv stbydly[1:0] pwronbdbnc[1:0] pwronrsten restarten 00 0 1 0 0 0 0 1c mema r/w 8'b0000_0000 mema[7:0] 00 0 0 0 0 0 0 1d memb r/w 8'b0000_0000 memb[7:0] 00 0 0 0 0 0 0 1e memc r/w 8'b0000_0000 memc[7:0] 00 0 0 0 0 0 0 1f memd r/w 8'b0000_0000 memd[7:0] 00 0 0 0 0 0 0 table 135. functional page bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0
analog integrated circuit device data 114 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description 20 sw1abvolt r/w/m 8'b00xx_xxxx ?? sw1ab[5:0] 00 x x x x x x 21 sw1abstby r/w 8'b00xx_xxxx ?? sw1abstby[5:0] 00 x x x x x x 22 sw1aboff r/w 8'b00xx_xxxx ?? sw1aboff[5:0] 00 x x x x x x 23 sw1abmode r/w 8'b0000_1000 ?? sw1abomode ? sw1abmode[3:0] 00 0 0 1 0 0 0 24 sw1abconf r/w 8'bxx00_xx00 sw1abdvsspeed[1:0] sw1baphase[1:0] sw1abfreq[1:0] ? sw1abilim xx 0 0 x x 0 0 2e sw1cvolt r/w 8'b00xx_xxxx ?? sw1c[5:0] 00 x x x x x x 2f sw1cstby r/w 8'b00xx_xxxx ?? sw1cstby[5:0] 00 x x x x x x 30 sw1coff r/w 8'b00xx_xxxx ?? sw1coff[5:0] 00 x x x x x x 31 sw1cmode r/w 8'b0000_1000 ?? sw1comode ? sw1cmode[3:0] 00 0 0 1 0 0 0 32 sw1cconf r/w 8'bxx00_xx00 sw1cdvsspeed[1:0] sw1cphase[1:0] sw1cfreq[1:0] ? sw1cilim xx 0 0 x x 0 0 35 sw2volt r/w 8'b0xxx_xxxx ? sw2[6:0] 0x x x x x x x 36 sw2stby r/w 8'b0xxx_xxxx ? sw2stby[6:0] 0x x x x x x x 37 sw2off r/w 8'b0xxx_xxxx ? sw2off[6:0] 0x x x x x x x 38 sw2mode r/w 8'b0000_1000 ?? sw2omode ? sw2mode[3:0] 00 0 0 1 0 0 0 39 sw2conf r/w 8'bxx01_xx00 sw2dvsspeed[1:0] sw2phase[1:0] sw2freq[1:0] ? sw2ilim xx 0 1 x x 0 0 3c sw3avolt r/w 8'b0xxx_xxxx ? sw3a[6:0] 0x x x x x x x 3d sw3astby r/w 8'b0xxx_xxxx ? sw3astby[6:0] 0x x x x x x x table 135. functional page bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0
analog integrated circuit device data freescale semiconductor 115 pf0100 functional block requirements and behaviors control interface i2c block description 3e sw3aoff r/w 8'b0xxx_xxxx ? sw3aoff[6:0] 0x x x x x x x 3f sw3amode r/w 8'b0000_1000 sw3aomode ? sw3amode[3:0] 00 0 0 1 0 0 0 40 sw3aconf r/w 8'bxx10_xx00 sw3advsspeed[1:0] sw3aphase[1:0] sw3afreq[1:0] ? sw3ailim xx 1 0 x x 0 0 43 sw3bvolt r/w 8'b0xxx_xxxx ? sw3b[6:0] 0x x x x x x x 44 sw3bstby r/w 8'b0xxx_xxxx ? sw3bstby[6:0] 0x x x x x x x 45 sw3boff r/w 8'b0xxx_xxxx ? sw3boff[6:0] 0x x x x x x x 46 sw3bmode r/w 8'b0000_1000 ?? sw3bomode ? sw3bmode[3:0] 00 0 0 1 0 0 0 47 sw3bconf r/w 8'bxx10_xx00 sw3bdvsspeed[1:0] sw3bphase[1:0] sw3bfreq[1:0] ? sw3bilim xx 1 0 x x 0 0 4a sw4volt r/w 8'b0xxx_xxxx ? sw4[6:0] 0x x x x x x x 4b sw4stby r/w 8'b0xxx_xxxx ? sw4stby[6:0] 0x x x x x x x 4c sw4off r/w 8'b0xxx_xxxx ? sw4off[6:0] 0x x x x x x x 4d sw4mode r/w 8'b0000_1000 ?? sw4omode ? sw4mode[3:0] 00 0 0 1 0 0 0 4e sw4conf r/w 8'bxx11_xx00 sw4dvsspeed[1:0] sw4phase[1:0] sw4freq[1:0] ? sw4ilim xx 1 1 x x 0 0 66 swbstctl r/w 8'b0xx0_10xx ? swbst1stbymode[1:0] ? swbst1mode[1:0] swbst1volt[1:0] 0x x 0 1 0 x x 6a vrefddrctl r/w 8'b000x_0000 ?? ? vrefddren ? ? ? ? 00 0 x 0 0 0 0 6b vsnvsctl r/w 8'b0000_0xxx ?? ? ? ? vsnvsvolt[2:0] 00 0 0 0 0 x x table 135. functional page bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0
analog integrated circuit device data 116 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description 6c vgen1ctl r/w 8'b000x_xxxx ? vgen1lpwr vgen1stby vgen1en vgen1[3:0] 00 0 x x x x x 6d vgen2ctl r/w 8'b000x_xxxx ? vgen2lpwr vgen2stby vgen2en vgen2[3:0] 00 0 x x x x x 6e vgen3ctl r/w 8'b000x_xxxx ? vgen3lpwr vgen3stby vgen3en vgen3[3:0] 00 0 x x x x x 6f vgen4ctl r/w 8'b000x_xxxx ? vgen4lpwr vgen4stby vgen4en vgen4[3:0] 00 0 x x x x x 70 vgen5ctl r/w 8'b000x_xxxx ? vgen5lpwr vgen5stby vgen5en vgen5[3:0] 00 0 x x x x x 71 vgen6ctl r/w 8'b000x_xxxx ? vgen6lpwr vgen6stby vgen6en vgen6[3:0] 00 0 x x x x x 7f page register r/w 8'b0000_0000 ?? ? page[4:0] 00 0 0 0 0 0 0 table 136. extended page 1 address register name type default bits[7:0] 7 6 5 4 3 2 1 0 80 otp fuse read en r/w 8'b000x_xxx0 ?? ? ? ??? otp fuse read en 00 0 x xxx0 84 otp load mask r/w 8'b0000_0000 start rl pwbrtn force pwrctl rl pwrctl rl otp rl otp ecc rl otp fuse rl trim fuse 00 0 0 0000 8a otp ecc se1 r 8'bxxx0_0000 ? ? ? ecc5_se ecc4_se ecc3_se ecc2_se ecc1_se xx x 0 0000 8b otp ecc se2 r 8'bxxx0_0000 ? ? ? ecc10_se ecc9_se ecc8_se ecc7_se ecc6_se xx x 0 0000 8c otp ecc de1 r 8'bxxx0_0000 ? ? ? ecc5_de ecc4_de ecc3_de ecc2_de ecc1_de xx x 0 0000 8d otp ecc de2 r 8'bxxx0_0000 ? ? ? ecc10_de ecc9_de ecc8_de ecc7_de ecc6_de xx x 0 0000 a0 otp sw1ab volt r/w 8'b00xx_xxxx ?? sw1ab_volt[5:0] 00 x x xxxx table 135. functional page bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0
analog integrated circuit device data freescale semiconductor 117 pf0100 functional block requirements and behaviors control interface i2c block description a1 otp sw1ab seq r/w 8'b000x_xxxx ? sw1ab_seq[4:0] 00 0 x xxxx a2 otp sw1ab config r/w 8'b0000_xxxx ?? ? ? sw1_config[1:0] sw1ab_freq[1:0] 00 0 0 xxxx a8 otp sw1c volt r/w 8'b00xx_xxxx ?? sw1c_volt[5:0] 00 x x xxxx a9 otp sw1c seq r/w 8'b000x_xxxx ? sw1c_seq[4:0] 00 0 x xxxx aa otp sw1c config r/w 8'b0000_00xx ?? ? ? ?? sw1c_freq[1:0] 00 0 0 00xx ac otp sw2 volt r/w 8'b0xxx_xxxx ? sw2_volt[5:0] 0x x x xxxx ad otp sw2 seq r/w 8'b000x_xxxx ?? sw2_seq[4:0] 00 0 x xxxx ae otp sw2 config r/w 8'b0000_00xx ?? ? ? ?? sw2_freq[1:0] 00 0 0 00xx b0 otp sw3a volt r/w 8'b0xxx_xxxx ? sw3a_volt[6:0] 0x x x xxxx b1 otp sw3a seq r/w 8'b000x_xxxx ?? sw3a_seq[4:0] 00 0 x xxxx b2 otp sw3a config r/w 8'b0000_xxxx ?? ? ? sw3_config[1:0] sw3a_freq[1:0] 00 0 0 xxxx b4 otp sw3b volt r/w 8'b0xxx_xxxx ? sw3b_volt[6:0] 0x x x xxxx b5 otp sw3b seq r/w 8'b000x_xxxx ?? sw3b_seq[4:0] 00 0 x xxxx b6 otp sw3b config r/w 8'b0000_00xx ?? ? ? ?? sw3b_config[1:0] 00 0 0 00xx b8 otp sw4 volt r/w 8'b00xx_xxxx ? sw4_volt[6:0] 00 x x xxxx b9 otp sw4 seq r/w 8'b000x_xxxx ?? ? sw4_seq[4:0] 00 0 x xxxx table 136. extended page 1 address register name type default bits[7:0] 7 6 5 4 3 2 1 0
analog integrated circuit device data 118 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description ba otp sw4 config r/w 8'b000x_xxxx ?? ? vtt ? ? sw4_freq[1:0] 00 0 x xxxx bc otp swbst volt r/w 8'b0000_00xx ?? ? ? ?? swbst_volt[1:0] 00 0 0 00xx bd otp swbst seq r/w 8'b0000_xxxx ?? ? swbst_seq[4:0] 00 0 0 xxxx c0 otp vsnvs volt r/w 8'b0000_0xxx ?? ? ? ? vsnvs_volt[2:0] 00 0 0 00xx c4 otp vrefddr seq r/w 8'b000x_x0xx ?? ? vrefddr_seq[4:0] 00 0 x x0xx c8 otp vgen1 volt r/w 8'b0000_xxxx ?? ? ? vgen1_volt[3:0] 00 0 0 xxxx c9 otp vgen1 seq r/w 8'b000x_xxxx ?? ? vgen1_seq[4:0] 00 0 x xxxx cc otp vgen2 volt r/w 8'b0000_xxxx ?? ? ? vgen2_volt[3:0] 00 0 0 xxxx cd otp vgen2 seq r/w 8'b000x_xxxx ?? ? vgen2_seq[4:0] 00 0 x xxxx d0 otp vgen3 volt r/w 8'b0000_xxxx ?? ? ? vgen3_volt[3:0] 00 0 0 xxxx d1 otp vgen3 seq r/w 8'b000x_xxxx ?? ? vgen3_seq[4:0] 00 0 x xxxx d4 otp vgen4 volt r/w 8'b0000_xxxx ?? ? ? vgen4_volt[3:0] 00 0 0 xxxx d5 otp vgen4 seq r/w 8'b000x_xxxx ?? ? vgen4_seq[4:0] 00 0 x xxxx d8 otp vgen5 volt r/w 8'b0000_xxxx ?? ? ? vgen5_volt[3:0] 00 0 0 xxxx d9 otp vgen5 seq r/w 8'b000x_xxxx ?? ? vgen5_seq[4:0] 00 0 x xxxx table 136. extended page 1 address register name type default bits[7:0] 7 6 5 4 3 2 1 0
analog integrated circuit device data freescale semiconductor 119 pf0100 functional block requirements and behaviors control interface i2c block description dc otp vgen6 volt r/w 8'b0000_xxxx ?? ? ? vgen6_volt[3:0] 00 0 0 xxxx dd otp vgen6 seq r/w 8'b000x_xxxx ?? ? vgen6_seq[4:0] 00 0 x xxxx e0 otp pu config1 r/w 8'b000x_xxxx ?? ? pwron_ cfg1 swdvs_clk1[1:0] seq_clk_speed1[1:0] 00 0 x xxxx e1 otp pu config2 r/w 8'b000x_xxxx ?? ? pwron_ cfg2 swdvs_clk2[1:0] seq_clk_speed2[1:0] 00 0 x xxxx e2 otp pu config3 r/w 8'b000x_xxxx ?? ? pwron_ cfg3 swdvs_clk3[1:0] seq_clk_speed3[1:0] 00 0 x xxxx e3 otp pu config xor r 8'b000x_xxxx ?? ? pwron_cfg _xor swdvs_clk3_xor seq_clk_speed_xor 00 0 x xxxx e4 otp fuse por1 r/w 8'b0000_00x0 tbb_por soft_fuse _por ???? fuse_por1 ? 00 0 0 00x0 e5 otp fuse por1 r/w 8'b0000_00x0 rsvd rsvd ? ? ? ? fuse_por2 ? 00 0 0 00x0 e6 otp fuse por1 r/w 8'b0000_00x0 rsvd rsvd ? ? ? ? fuse_por3 ? 00 0 0 00x0 e7 otp fuse por xor r 8'b0000_00x0 rsvd rsvd ? ? ? ? fuse_por_ xor ? 00 0 0 00x0 e8 otp pwrgd en r/w/m 8'b0000_000x ?? ? ? ???otp_pg_en 00 0 0 00x0 f0 otp en ecco r/w 8'b000x_xxxx ?? ? en_ecc_ bank5 en_ecc_ bank4 en_ecc_ bank3 en_ecc_ bank2 en_ecc_ bank1 00 0 x xxxx f1 otp en ecc1 r/w 8'b000x_xxxx ?? ? en_ecc_ bank10 en_ecc_ bank9 en_ecc_ bank8 en_ecc_ bank7 en_ecc_ bank6 00 0 x xxxx f4 otp spare2_4 r/w 8'b0000_xxxx ?? ? ? rsvd 00 0 0 xxxx f5 otp spare4_3 r/w 8'b0000_0xxx ?? ? ? ? rsvd 00 0 0 0xxx table 136. extended page 1 address register name type default bits[7:0] 7 6 5 4 3 2 1 0
analog integrated circuit device data 120 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description f6 otp spare6_2 r/w 8'b0000_00xx ?? ? ? ?? rsvd 00 0 0 00xx f7 otp spare7_1 r/w 8'b0000_0xxx ?? ? ? ? ? ? rsvd 00 0 0 0xxx fe otp done r/w 8'b0000_000x ?? ? ? ??? otp_done 00 0 0 000x ff otp i2c addr r/w 8'b0000_0xxx ?? ? ? i2c_slv addr[3:0] 00 0 0 1xxx table 137. extended page 2 address register name type default bits[7:0] 7 6 5 4 3 2 1 0 81 sw1ab pwrstg r/w 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw1ab_pwrstg[2:0] 11 1 11111 82 pwrstg rsvd r 8'b0000_0000 pwrstgrsvd 00 0 00000 83 sw1c pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw1c_pwrstg[2:0] 11 1 11111 84 sw2 pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw2_pwrstg[2:0] 11 1 11111 85 sw3a pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw3a_pwrstg[2:0] 11 1 11111 86 sw3b pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw3b_pwrstg[2:0] 11 1 11111 87 sw4 pwrstg r 8'b0111_1111 fslext_ therm_ disable pwrgd_ shdwn_ disable rsvd rsvd rsvd sw4_pwrstg[2:0] 00 1 11111 88 pwrctrl otp ctrl r 8'b0000_0001 ?? ? ??? pwrgd_en otp_ shdwn_en 00 0 00001 8d i2c write address trap r/w 8'b0000_0000 i2c_write_address_trap[7:0] 00 0 00000 8e i2c trap page r/w 8'b0000_0000 let_it_ roll rsvd rsvd i2c_trap_page[4:0] 00 0 00000 table 136. extended page 1 address register name type default bits[7:0] 7 6 5 4 3 2 1 0
analog integrated circuit device data freescale semiconductor 121 pf0100 functional block requirements and behaviors control interface i2c block description 8f i2c trap cntr r/w 8'b0000_0000 i2c_write_address_counter[7:0] 00 0 00000 90 io drv r/w 8'b00xx_xxxx sda_drv[1:0] sdwnb_drv[1:0] intb_drv[1:0] resetbmcu_drv[1:0] 00 x xxxxx do otp auto ecc0 r/w 8'b0000_0000 ?? ? auto_ecc _bank5 auto_ecc _bank4 auto_ecc_ bank3 auto_ecc _bank2 auto_ecc_ bank1 00 0 00000 d1 otp auto ecc1 r/w 8'b0000_0000 ?? ? auto_ecc_ bank10 auto_ecc _bank9 auto_ecc_ bank8 auto_eccb ank7 auto_ecc_ bank6 00 0 00000 d8 otp auto prog0 r/w 8'b0000_0000 prog_time[1:0] rsvd auto_fuse _prog5 auto_fuse _prog4 auto_fuse prog3 auto_fuse _prog2 auto_fuse _prog1 00 0 00000 d9 otp auto prog1 r/w 8'b0000_0000 start reload en_rw auto_fuse _prog10 auto_fuse _prog9 auto_fuse _prog8 auto_fuse _prog7 auto_fuse _prog6 00 0 00000 e1 otp ecc ctrl1 r/w 8'b0000_0000 ecc1_en_ tbb ecc1_calc _cin ecc1_cin_tbb[5:0] 00 0 00000 e2 otp ecc ctrl2 r/w 8'b0000_0000 ecc2_en_ tbb ecc2_calc _cin ecc2_cin_tbb[5:0] 00 0 00000 e3 otp ecc ctrl3 r/w 8'b0000_0000 ecc3_en_ tbb ecc3_calc _cin ecc3_cin_tbb[5:0] 00 0 00000 e4 otp ecc ctrl4 r/w 8'b0000_0000 ecc4_en_ tbb ecc4_calc _cin ecc4_cin_tbb[5:0] 00 0 00000 e5 otp ecc ctrl5 r/w 8'b0000_0000 ecc5_en_ tbb ecc5_calc _cin ecc5_cin_tbb[5:0] 00 0 00000 e6 otp ecc ctrl6 r/w 8'b0000_0000 ecc6_en_ tbb ecc6_calc _cin ecc6_cin_tbb[5:0] 00 0 00000 e7 otp ecc ctrl7 r/w 8'b0000_0000 ecc7_en_ tbb ecc7_calc _cin ecc7_cin_tbb[5:0] 00 0 00000 e8 otp ecc ctrl8 r/w 8'b0000_0000 ecc8_en_ tbb ecc8_calc _cin ecc8_cin_tbb[5:0] 00 0 00000 table 137. extended page 2 address register name type default bits[7:0] 7 6 5 4 3 2 1 0
analog integrated circuit device data 122 freescale semiconductor pf0100 functional block requi rements and behaviors control interface i2 c block description e9 otp ecc ctrl9 r/w 8'b0000_0000 ecc9_en_ tbb ecc9_calc _cin ecc9_cin_tbb[5:0] 00 0 00000 ea otp ecc ctrl10 r/w 8'b0000_0000 ecc10_en_ tbb ecc10_cal c_cin ecc10_cin_tbb[5:0] 00 0 00000 f1 otp fuse ctrl1 r/w 8'b0000_0000 ?? ? ? antifuse1_ en antifuse1_ load antifuse1_ rw bypass1 00 0 0 0 0 00 f2 otp fuse ctrl2 r/w 8'b0000_0000 ?? ? ? antifuse2_ en antifuse2_ load antifuse2_ rw bypass2 00 0 0 0 0 00 f3 otp fuse ctrl3 r/w 8'b0000_0000 ?? ? ? antifuse3_ en antifuse3_ load antifuse3_ rw bypass3 00 0 0 0 0 00 f4 otp fuse ctrl4 r/w 8'b0000_0000 ?? ? ? antifuse4_ en antifuse4_ load antifuse4_ rw bypass4 00 0 0 0 0 00 f5 otp fuse ctrl5 r/w 8'b0000_0000 ?? ? ? antifuse5_ en antifuse5_ load antifuse5_ rw bypass5 00 0 0 0 0 00 f6 otp fuse ctrl6 r/w 8'b0000_0000 ?? ? ? antifuse6_ en antifuse6_ load antifuse6_ rw bypass6 00 0 0 0 0 00 f7 otp fuse ctrl7 r/w 8'b0000_0000 ?? ? ? antifuse7_ en antifuse7_ load antifuse7_ rw bypass7 00 0 0 0 0 00 f8 otp fuse ctrl8 r/w 8'b0000_0000 ?? ? ? antifuse8_ en antifuse8_ load antifuse8_ rw bypass8 00 0 0 0 0 00 f9 otp fuse ctrl9 r/w 8'b0000_0000 ?? ? ? antifuse9_ en antifuse99 _load antifuse9_ rw bypass9 00 0 0 0 0 00 fa otp fuse ctrl10 r/w 8'b0000_0000 ?? ? ? antifuse10 _en antifuse10 _load antifuse10 _rw bypass10 00 0 00000 table 137. extended page 2 address register name type default bits[7:0] 7 6 5 4 3 2 1 0
analog integrated circuit device data freescale semiconductor 123 pf0100 typical applications introduction 8 typical applications 8.1 introduction figure 28 provides a typical application diagram of the pf0100 pmic together with its functional components. for details on component references and additional components such as filters, refer to the individual sections. 8.1.1 application diagram vin intb licell swbstfb swbstin swbstlx o/p drive swbst 600 ma boost pwron standby ictest output pin input pin bi-directional pin package pin legend scl sda vddio sw3a/b single/dual ddr 2500 ma buck vcoredig vcoreref sdwnb gndref 100n coin cell battery 1u 220n vin 2 x 22uf swbst output 2.2uf 10uf vin to/from ap sw1cfb sw1ain sw1c 2000 ma buck sw1fb sw1alx sw1blx sw1a/b single/dual 2500 ma buck sw1vsssns 1.0uh 2 x22uf sw1ab output vin 4.7uf vsnvs vsnvs 0.47u li cell charger resetbmcu sw2 2000 ma buck vgen1 100ma vgen1 vin1 2.2u vgen2 250ma vgen2 4.7u vgen3 100ma vgen3 vin2 2.2u vgen4 350ma vgen4 4.7u vgen5 100ma vgen5 vin3 2.2u vgen6 200ma vgen6 2.2u best of supply otp 100k sw4 1000 ma buck vrefddr 1u vddotp vinrefddr vhalf 100n 100n vcore 100k 100k 4.7k pf0100 control clocks 32khz and 16mhz initialization state machine i2c interface clocks and resets i2c register map trim-in-package 4.7k 1u o/p drive o/p drive vin sw1bin 4.7uf sw1clx o/p drive sw1cin 4.7uf 1.0uh sw1c output 22uf vin sw2fb sw2lx o/p drive sw2in 4.7uf 1.0uh sw2 output 22uf vin sw2in sw3ain sw3afb sw3alx sw3blx 1.0uh 22uf sw3a output vin 4.7uf o/p drive o/p drive sw3bin 4.7uf vin sw3b output sw3bfb 22uf 1.0uh sw3vsssns sw4in sw4fb sw4lx 1.0uh 2 x 22uf sw4 output vin 4.7uf o/p drive supplies control dvs control dvs control reference generation vsw3a vin core control logic vin1 vin2 vin3 vddotp vsw2 vsw2 vsw2 1.0u 1.0u 1.0u gndref1 figure 28. typical application schematic
analog integrated circuit device data 124 freescale semiconductor pf0100 typical applications introduction 8.1.2 bill of material the following table provides a complete list of the recomme nded components on a full featured system using the pf0100 device. critical components such as inductors, tr ansistors, and diodes are provided with a recommended part number, but equivalent components may be used. table 138. bill of material (68) value qty description part# manufacturer component/pin pmic 1 power management ic MMPF0100 freescale buck, sw1ab - (0.300-1.875 v), 2.5 a 1.0 p h1 4 x 4 x 2.1 i sat = 4.5 a for 10% drop, dcr max = 11.9 m : xfl4020-102meb coilcraft output inductor 1.0 p h? 5 x 5 x 1.5 i sat = 3.6 a for 10% drop, dcr max = 50 m : lps5015_102ml coilcraft output inductor optional 22 p f 4 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 p f 1 10 v x5r 0603 lmk107bj475ka-t taiyo yuden input capacitance 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance buck, sw1c- (0.300-1.875 v), 2.0 a 1.0 p h1 4 x 4 x 1.2 i sat = 2.8 a for 10% drop, dcr max = 60 m : lps4012-102nl coilcraft output inductor 1.0 p h? 3x 3 1.2 i sat = 2.5 a for 10% drop, dcr max = 42 m : xfl3012-102ml coilcraft output inductor optional 22 p f 2 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 p f 1 10 v x5r 0603 lmk107bj475ka-t taiyo yuden input capacitance 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance buck, sw2- (0.400-3.300 v), 2.0 a 1.0 p h1 4 x 4 x 1.2 i sat = 2.8 a for 10% drop, dcr max = 60 m : lps4012-102nl coilcraft output inductor 1.0 p h? 3x 3 1.2 i sat = 2.5 a for 10% drop, dcr max = 42 m : xfl3012-102ml coilcraft output inductor optional 22 p f 2 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 p f 1 10 v x5r 0603 lmk107bj475ka-t taiyo yuden input capacitance 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance buck, sw3ab - (0.400-3.300 v), 2.5 a 1.0 p h1 4 x 4 x 2.1 i sat = 4.5 a for 10% drop, dcr max = 11.9 m : xfl4020-102meb coilcraft output inductor 1.0 p h? 5 x 5 x 1.5 i sat = 3.6 a for 10% drop, dcr max = 50 m : lps5015_102ml coilcraft output inductor optional
analog integrated circuit device data freescale semiconductor 125 pf0100 typical applications introduction 22 p f 4 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 p f 1 10 v x5r 0603 lmk107bj475ka-t taiyo yuden input capacitance 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance buck, sw4 - (0.400-3.300v), 1a 1.0 p h1 2.5 x 2 x 1 i sat = 1.8 a for 30% drop, dcr max = 84 m : vls252010et-1r0n tdk output inductor 1.0 p h- 2.2 x 2.1 x 1 i sat = 1.2 a for 10% drop, dcr max = 89 m : xpl2010_102ml coilcraft output inductor optional 22 p f 2 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 p f 1 10 v x5r 0603 lmk107bj475ka-t taiyo yuden input capacitance 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance boost, swbst - 5.0 v, 600 ma 2.2 p h? 3 x 3 x 1.5 i sat = 2.0 a for 10% drop, dcr max = 110 m : lps3015-222ml coilcraft output inductor 22 p f 2 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 10 p f 1 10 v x5r 0805 c2012x5r1a106mt tdk input capacitance 2.2 p f 1 6.3 v x5r 0402 c0402c225m9pactu kemet input capacitance 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance 1.0 a 1 20 v sod-123fl mbr120vlsft1g on semiconductor schottky diode ldo, vgen1 - (0.80-1.55), 100 ma 2.2 p f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america input capacitance ldo, vgen2 - (0.80-1.55), 250 ma 4.7 p f 1 6.3 v x5r 0402 c0402x5r6r3-475mnp venkel output capacitance ldo, vgen3 - (1.80-3.30), 100 ma 2.2 p f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america input capacitance ldo, vgen4 - (1.80-3.30), 350 ma 4.7 p f 1 6.3 v x5r 0402 c0402x5r6r3-475mnp venkel output capacitance ldo, vgen5 - (1.80-3.30), 150 ma 2.2 p f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america input capacitance ldo, vgen6 - (1.80-3.30), 200 ma 2.2 p f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance ldo/switch vsnvs - (1.1-3.3), 200 ma 0.47 p f 1 6.3 v x5r 0402 c1005x5r0j474k tdk output capacitance table 138. bill of material (68) value qty description part# manufacturer component/pin
analog integrated circuit device data 126 freescale semiconductor pf0100 typical applications pf0100 layout guidelines 8.2 pf0100 layout guidelines 8.2.1 general board recommendations 1. it is recommended to use an eight layer board stack-up arranged as follows: ? high current signal ?gnd ?signal ? power ? power ?signal ?gnd ? high current signal 2. allocate top and bottom pcb layers for power rout ing (high current signals), copper-pour the unused area. 3. use internal layers sandwiched between two gnd planes for the signal routing. 8.2.2 component placement it is desirable to keep all component rela ted to the power stage as close to the pmic as possible, specially decoupling input a nd output capacitors. reference, vrefddr - (0.20-1.65v), 10 ma 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america output capacitance 0.1 p f 2 10 v x5r 0402 c0402c104k8pac kemet vhalf, vinrefddr internal references, vcoredig, vcoreref, vcore 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america vcoredig 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america vcore 0.22 p f 1 10 v x5r 0402 grm155r61a224ke19d murata vcoreref coin cell 0.1 p f 1 10 v x5r 0402 c0402c104k8pac kemet licell miscellaneous 1.0 p f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america vin 100 k : 1 1/16 w 0402 rk73h1ettp1003f koa speer pwron 100 k : 1 1/16 w 0402 rk73h1ettp1003f koa speer resetbmcu 100 k : 1 1/16 w 0402 rk73h1ettp1003f koa speer sdwn 100 k : 1 1/16 w 0402 rk73h1ettp1003f koa speer intb notes 68. freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circu it drawings or tables. while freescale offers component recommendations in this configuration, it is the cust omer?s responsibility to valid ate their application. table 138. bill of material (68) value qty description part# manufacturer component/pin
analog integrated circuit device data freescale semiconductor 127 pf0100 typical applications pf0100 layout guidelines 8.2.3 general routing requirements 1. some recommended things to keep in mind for manufacturability: ? via in pads require a 4.5 mil minimum annular ring. pad must be 9.0 mils larger than the hole ? maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper ? minimum allowed spacing between line and hole pad is 3.5 mils ? minimum allowed spacing between line and line is 3.0 mils 2. care must be taken with swxfb pins traces. these signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the swxin, swx, swxlx, swbstin , swbst, and swbstlx pins. they could be also shielded. 3. shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. avoid coupling traces between important signal/low no ise supplies (like refcore, vcore, vcoredig) from any switching node (i.e. sw1alx, sw2lx, sw3lx, sw4alx, sw4blx, and swbstlx). 5. make sure that all components related to a specif i c block are referenced to the corresponding ground. 8.2.4 parallel routing requirements 1. i 2 c signal routing ? clk is the fastest signal of the system, so it must be given special care. ? to avoid contamination of these delicate signals by near by hi gh power or high frequency signals, it is a good practice to shield them with ground planes placed on adja cent layers. make sure the ground plane is uniform throughout the whole signal trace length. figure 29. recommended shielding for critical signals. ? these signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground pla ne. ? care must be taken with these signals not to contamin a te analog signals, as they are high frequency signals. another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
analog integrated circuit device data 128 freescale semiconductor pf0100 typical applications pf0100 layout guidelines 8.2.5 switching regulator layout recommendations 1. per design, the switching regulators in pf 0100 are designed to operate with only one input bulk capacitor. however, it is recommended to add a high frequency filter input capacitor (cin _hf), to filter out any noise at the regulator input. this capacitor should be in the range of 100 nf and should be placed right next to or under the ic, closest to the ic pins. 2. make high-current ripple traces low-inductance (short, high w/l ratio). 3. make high-current traces wide or copper islands. 4. make high-current traces symetrical fo r dual?phase regulators (sw1, sw3). diver controller swxin swxlx swxfb c out c in l swx vin compensation c in_hf figure 30. generic buck regulator architecture swxin inductor c in c out c in_hf swxlx gnd swxfb figure 31. recommended layout for buck regulators
analog integrated circuit device data freescale semiconductor 129 pf0100 typical applications thermal information 8.3 thermal information 8.3.1 rating data the thermal rating data of the packages has been simulated with the results listed in table 5 . junction to ambient thermal resistance nomenclatu re: the jedec spec ification reserves the symbol r
analog integrated circuit device data 130 freescale semiconductor pf0100 packaging packaging dimensions 9 packaging 9.1 packaging dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number. see the thermal characteristics section for specific thermal characteristics for each package. table 139. package drawing information package suffix package outline drawing number 56 qfn 8x8 mm - 0.5 mm pitch. e-type (full lead) ep 98asa00405d
ep suffix 56-pin qfn 98asa00405d issue 0 analog integrated circuit device data freescale semiconductor 131 pf0100 packaging packaging dimensions
ep suffix 56-pin qfn 98asa00405d issue 0 analog integrated circuit device data 132 freescale semiconductor pf0100 packaging packaging dimensions
ep suffix 56-pin qfn 98asa00405d issue 0 analog integrated circuit device data freescale semiconductor 133 pf0100 packaging packaging dimensions
analog integrated circuit device data 134 freescale semiconductor pf0100 reference section reference documents 10 reference section 10.1 reference documents table 140. pf0100 reference documents reference description an4536 MMPF0100 otp programming instructions
analog integrated circuit device data freescale semiconductor 135 pf0100 revision history document changes 11 revision history 11.1 document changes revision date description of changes 1.0 7/2011 ? preliminary specif ication release 2.0 8/2012 ? npi phase: prototype major updates throughout cycle 3.0 10/2012 ? initial production release
document number: MMPF0100 rev. 3.0 10/2012 information in this document is provided solely to enable system and software implementers to use freescale products. t here are no express or implied copyright licenses granted hereunder to design or fabric ate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the applic ation or use of any product or circuit, and specifically disclaims any and all liability, including with out limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. free scale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/p olicy.aspx?selector=rt&s=str0326182960&pc. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c- ware, energy efficient solutions logo, kinetis, mobilegt, po werquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of thei r respective owners. ? 2012 freescale semiconductor, inc.

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